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Behavior Modification Wristwatch
A wristwatch including a watch band and a watch body having an octagon shaped perimeter and being red in color and having the word STOP thereon to resemble a stop sign.
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| Number | Title | Issue Date |
| RE43359 | System and method for low power searching in content addressable memories using sampling search words to save power in compare lines An invention is provided for low Low power searching in a CAM using uses sample words to save power in the compare lines. The invention A method includes comparing a sample section of stored data to a corresponding sample section of search data on a plurality of row... | 05/08/2012 |
| 8169807 | Content addressable memory device having match line equalizer circuit In a content addressable memory device, before search operations in two TCAM cells connected to first and second match lines, respectively, a memory controller connects the first match line to a power source and connects the second match line to a ground, and then c... | 05/01/2012 |
| 7957171 | Associative memory and searching system using the same Associative memories capable of outputting multiple reference data close to search data are provided. A memory array compares each of the multiple reference data with the search data in parallel and generates multiple comparison current signals representing the resu... | 06/07/2011 |
| 7889530 | Reconfigurable content-addressable memory A system for determining memory addresses including a first content-addressable memory (CAM) configured to generate a first matchvector based on a first key; a first inverse-mask-reverse (IMR) module operatively connected to the first CAM, where the first IMR module... | 02/15/2011 |
| 7859876 | Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. ... | 12/28/2010 |
| 7830691 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 11/09/2010 |
| 7697311 | Storage apparatus, controller and control method Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage exte... | 04/13/2010 |
| 7688609 | Content addressable memory having dynamic match resolution A content addressable memory (CAM) architecture. For one embodiment, the CAM architecture includes a plurality of rows of CAM cells, each row configured to generate match results on a corresponding match line, a number of comparand lines, each coupled to a correspon... | 03/30/2010 |
| 7688610 | Low power match-line sensing circuit A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisi... | 03/30/2010 |
| 7606054 | Cache hit logic of cache memory and processor chip having the same A processor chip having a cache hit logic for determining whether data required by a processor is stored in a cache memory includes a dummy cell string that operates the same as a sense amplifier for sensing a tag address stored in a tag memory cell array and a comp... | 10/20/2009 |
| 7561454 | Compare circuit for a content addressable memory cell A ternary content addressable memory (CAM) cell is disclosed for providing reduced or minimized matchline (ML) capacitance and for increasing current between matchline and tail-line in the case of a mismatch. The speed of a CAM cell is generally inversely proportion... | 07/14/2009 |
| 7545660 | Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. ... | 06/09/2009 |
| 7522438 | Method and apparatus for CAM with reduced cross-coupling interference A method and apparatus for a CAM with reduced cross-coupling interference have been disclosed. ... | 04/21/2009 |
| 7511980 | Low power match-line sensing circuit A low power matchline sensing scheme where power is distributed according to the number of mismatching bits occurring on a matchline is disclosed. In particular, match decisions involving a larger number of mismatched bits consume less power compared to match decisi... | 03/31/2009 |
| 7499302 | Noise reduction in a CAM memory cell A dynamic CAM cell has features that reduce the effect of noise within a CAM array. By shielding the matchline from the wordline, noise transmitted from the matchline to the wordline is reduced. By placing the searchline equally distant from a bitline and the bitlin... | 03/03/2009 |
| 7483283 | Apparatus for efficient streaming data access on reconfigurable hardware and method for automatic generation thereof A content addressable memory (CAM) is disclosed that includes a memory having a first port configured to write a 1-bit data to the memory and a second port configured to read and write N-bit data. To update the CAM, an N-bit zero data word is written to the second p... | 01/27/2009 |
| 7466576 | Technique for CAM width expansion using an external priority encoder A technique that provides width expansion of two CAMs of varying widths by combining match results from two CAMs by integrating the two CAMs. In one embodiment, a synchronizer circuit triggers the operation of an External Priority Encoder module which can be used to... | 12/16/2008 |
| 7460382 | Flash memory module A device is fabricated on a flash process semiconductor die. The device includes main memory to store processor information. A cache memory caches a portion of the processor information. A cache controller controls the cache memory. A device interface communicates t... | 12/02/2008 |
| 7460383 | Storage apparatus, controller and control method Proposed is a highly reliable storage apparatus with fast access speed and low power consumption, as well as a controller and control method for controlling such a storage apparatus. This storage apparatus is equipped with a flash memory that provides a storage exte... | 12/02/2008 |
| 7447052 | Method and device for limiting current rate changes in block selectable search engine A search engine system can include at least one command decoder having search engine command input and at least one pipeline for propagating command data from the command decoder from a pipeline input to a pipeline output. The command data can be directed to targete... | 11/04/2008 |
| 7436688 | Priority encoder circuit and method A priority encoder circuit can include a number of sectional encoder circuits that each encode “m” inputs signals into sets of “P” encoder outputs, where m>p. Each sectional encoder circuit can also output a group indication signal representing the activatio... | 10/14/2008 |
| 7433217 | Content addressable memory cell configurable between multiple modes and method therefor A CAM cell (200) can include a compare section (206) and a configuration section (208). In a binary mode of operation, two compare data values can be driven on value lines VL1 to VL4 (216-0 to 216-3) for comparison ag... | 10/07/2008 |
| 7426127 | Full-rail, dual-supply global bitline accelerator CAM circuit A content-addressable memory circuit includes a first local bit line coupled to a first memory location, a second local bit line coupled to a second memory location, a global bit line coupled to the first and second local bit lines and a global bit line accelerator ... | 09/16/2008 |
| 7417882 | Content addressable memory device A content addressable memory (CAM) device can include a plurality CAM cell groups. The CAM cells of each group can be commonly connected to at least one local compare data line. A mask value circuit can be provided corresponding to each CAM cell group. Each mask val... | 08/26/2008 |
| 7417881 | Low power content addressable memory A low power content addressable memory (CAM) device. The CAM device receives an N-bit comparand value and, in response, activates less than N compare lines within the CAM device to compare each of the N bits of the comparand value with contents of CAM cells coupled ... | 08/26/2008 |
| 7406561 | Data coding system and method A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems. ... | 07/29/2008 |
| 7403407 | Magnitude comparator circuit for content addressable memory with programmable priority selection A magnitude comparator circuit can include a bitwise comparison section that includes two passgates for each bit of two values that are compared to one another. The passgates can be enabled according to corresponding bit values of the two values. ... | 07/22/2008 |
| 7397682 | Associative memory having a mask function for use in network devices and network system An associative memory carries out a search operation in plural fields. The search data 3-1 through 3-r in fields, r in number, are supplied to the primary associative memories 20-1 through 20-r. The i-th primar... | 07/08/2008 |
| 7388768 | Semiconductor device Control clocks of different phases are distributed to a memory array divided into multiple banks, and processing of entries and search keys (read and write operations and search operation) is performed at different phases. The memory array divided into banks is furt... | 06/17/2008 |
| 7386660 | CAM with automatic writing to the next free address A method and apparatus for automatically writing non-matching data to a non-valid location within a Content Addressable Memory (CAM) is disclosed. The non-valid locations are determined simultaneously with a search process for a matching address, so that in the even... | 06/10/2008 |
| 7382637 | Block-writable content addressable memory device A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the m... | 06/03/2008 |
| 7382638 | Matchline sense circuit and method A matchline sense circuit for detecting a rising voltage on a matchline of a CAM array is disclosed. The circuit initially precharges a matchline to ground before turning on a current source to supply current to the matchline and raise the voltage of the matchline. ... | 06/03/2008 |
| 7379314 | Content addressable memory (CAM) architecture An improved Content Addressable Memory (CAM) architecture and method for operating the same is provided herein. The improved CAM architecture may generally include an array of memory cells arranged into rows and columns, where each row includes a number of memory ce... | 05/27/2008 |
| 7379372 | Non-volatile memory device with scanning circuit and method An accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device including a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having ... | 05/27/2008 |
| 7376877 | Combined tag and data ECC for enhanced soft error recovery from cache tag errors A computer data signal comprises a first code group and a second code group. The first code group has a first symbol and an error detection code for the first symbol. The second code group has a second symbol different from the first symbol and an error correction c... | 05/20/2008 |
| 7376791 | Memory access systems and methods for configuring ways as cache or directly addressable memory A memory system is described. A processor provides a data access address, and selectively configures a selected number of the ways of a memory device as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belong... | 05/20/2008 |
| 7373454 | Pattern detect and byte align circuit using CAM A method detects a programmable pattern (e.g., Ethernet comma or SONET A1A2 frame) and simultaneously byte aligns to that pattern. The technique uses a content addressable memory (CAM) programmed (e.g., selected by the user) with a particular pattern to enable detec... | 05/13/2008 |
| 7372713 | Match sensing circuit for a content addressable memory device A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all... | 05/13/2008 |
| 7369454 | Semiconductor integrated circuit device A semiconductor integrated circuit device comprises several blocks including a word line connected with a memory cell, a row decoder selecting the word line, and a block decoder selecting the block. The block decoder includes a logical address register holding logic... | 05/06/2008 |
| 7370134 | System and method for memory hub-based expansion bus A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupl... | 05/06/2008 |
