Class 365/241 - Detectors

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter where the memory locations are detected one
No. of patents: 36
Last issue date: 02/16/2010

Number	Title	Issue Date
7663967	Semiconductor memory device having a plurality of chips and capability of outputting a busy signal One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy ...	02/16/2010
7391632	Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complex...	06/24/2008
RE40252	Flash memory control method, flash memory system using the control method and flash memory device using the control method A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absence of an err...	04/22/2008
7180799	Circuit for setting one of a plurality of organization forms of an integrated circuit and method for operating it A circuit for setting one of a plurality of organization forms of an integrated circuit includes a detector circuit connected to an external connection of the integrated circuit. The external connection in at least one of the organization forms can be used for exter...	02/20/2007
7164611	Data retention kill function A secure memory device that is configured to prevent unauthorized access of data is disclosed. More specifically, a kill function logic device is capable of initiating security measures upon the occurrence of some event. The security measures may include disabling r...	01/16/2007
7098833	Tri-value decoder circuit and method A tri-value decoder and method for decoding at least three states of an input signal are provided. An exemplary tri-value decoder and method can facilitate decoding of input signals without the use of threshold values and/or forcing a tri-state input signal to a mid...	08/29/2006
7050353	Semiconductor memory having burst transfer function A refresh control circuit generates a refresh request in a predetermined cycle. A first burst control circuit outputs a predetermined number of strobe signals in accordance with an access command. A burst access operation is executed by an access command. A data inp...	05/23/2006
6977854	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	12/20/2005
6977853	Flash array implementation with local and global bit lines A flash memory device that can detect short circuits in local and global bit lines. The flash memory device has a plurality of sets of adjacent local bit lines, a plurality of global bit lines and a plurality of select transistors. Each select transistor has a contr...	12/20/2005
6956789	Cycle ready circuit for self-clocking memory device A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memor...	10/18/2005
6894939	Data processor, semiconductor memory device and clock frequency detecting method In a data processor which comprises a semiconductor memory device, a potential on a bit line of the semiconductor memory device is monitored at the end of a precharge, required for the semiconductor memory device, to detect an anomalous frequency of a clock applied ...	05/17/2005
6661717	Dynamically centered setup-time and hold-time window An apparatus and method for dynamically centering a setup-time and hold-time window. An access window defined by a setup-time and a hold-time is determined. A determination is made whether the access window is centered about a centerline. The centerline i...	12/09/2003
6646950	High speed decoder for flash memory A word line driver for flash memories using NMOS circuitry to reduce parasitic capacitance loading on boost circuitry in low-voltage applications. A delay scheme which delays turn-on of the driver's source-drain circuit for a short time after the turn-on ...	11/11/2003
6631094	Semiconductor memory device having SRAM interface A semiconductor memory device includes a latch circuit which latches an address signal supplied from an exterior of the device, a core circuit which includes memory cells, to which access is made at the address stored in the latch circuit, and a latch tim...	10/07/2003
6522589	Semiconductor apparatus and mode setting method for semiconductor apparatus In a semiconductor apparatus, the first voltage detection circuit is configured to judge whether a potential of the input signal is higher or lower than a first reference potential, and output a first level signal if the potential of the input signal is j...	02/18/2003
6434079	Semiconductor memory device for distributing load of input and output lines A semiconductor memory device for distributing load of input and output lines includes: a line pre-charger for pre-charging a global read line composed of a pair of lines to a high level in an initial or steady state, a plurality of memory banks connected...	08/13/2002
6285583	High speed sensing to detect write protect state in a flash memory device A flash memory device (100) includes a core cell array including two banks (194, 196) of core cells and address decoding circuitry (112, 114, 118, 120) and a write protect circuit. The write protect circuit includes sector write protect circuits (210) ass...	09/04/2001
6233201	Voltage monitoring circuit and memory card incorporating the same A voltage monitoring circuit compares a voltage, which is obtained by dividing the voltage required for writing or erasing data to or from a semiconductor storage device, with a reference voltage (Vref) using a comparator, and if the comparison result ind...	05/15/2001
6185134	Flash memory control method, flash memory system using the control method and flash memory device using the control method A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absenc...	02/06/2001
6147927	Synchronous semiconductor memory device capable of more reliable communication of control signal and data In an SDRAM, an unlocked-state detection circuit detects whether synchronization between an external clock signal and an internal clock signal generated in the SDRAM according to the external clock signal is locked. When the internal clock signal is inapp...	11/14/2000
6141262	Boosting circuit with boosted voltage limited A boosting circuit includes a plurality of boosting circuit units, a voltage detecting circuit and a boost control circuit. The plurality of boosting circuit units have their outputs connected together and respectively having voltage boosting functions. E...	10/31/2000
6101133	Apparatus and method for preventing accidental writes from occurring due to simultaneous address and write enable transitions A Random Access Memory (RAM) with improved memory access time supporting simultaneous transitions of an address signal and a write enable signal while preventing accidental writes. The RAM includes a memory array, an address transition detector and a race...	08/08/2000
6078546	Synchronous semiconductor memory device with double data rate scheme Disclosed is a synchronous semiconductor device having a double data rate input circuit which allows data to be written in the device in response to a clock signal and a data strobe signal. The input circuit stores a pair of data which is synchronized wit...	06/20/2000
6061274	Methods and apparatus for message transfer in computer storage system A computer storage system includes an array of storage devices, a system cache memory, one or more back end directors for controlling data transfer between the storage devices and the system cache memory, and one or more front end directors for controllin...	05/09/2000
6058047	Semiconductor memory device having error detection and correction A semiconductor memory device including a semiconductor memory having a memory region divided into a plurality of blocks including backup blocks, the number of writes to each block being limited, and a memory controller for reading data from the semicondu...	05/02/2000
6049490	Decoded signal comparison circuit A decoded signal comparison circuit comprises a plurality of decoders, each decoding address signals input in units of at least two bits, the address signals having bits which are input time-sequentially. It also comprises a first register group including...	04/11/2000
5943291	Method and apparatus for signal transition detection in integrated circuits A transition detection circuit includes a low-to-high detector and a high-to-low detector. Each of the detectors includes a normally closed switch that directly transmits an input signal and a delay block that transmits the input signal to control input o...	08/24/1999
5896324	Overvoltage detection circuit for generating a digital signal for a semiconductor memory device in parallel test mode A method for detecting an overvoltage signal applied to a semiconductor memory device address pin reduces stress on the device and simplifies the testing process by dividing the voltage of the overvoltage signal and comparing it to a reference voltage, th...	04/20/1999
5097447	Semiconductor memory device having a serial access memory A semiconductor memory device includes a RAM and a serial access memory (SAM). The SAM includes an address counter which generates a slave address and a master address. The slave address precedes the master address by half the period of a serial access st...	03/17/1992
4932002	Bit line latch sense amp A bit line latch sense amp is disclosed which substantially eliminates a number of problems associated with prior art sensing schemes which result through asymmetrical operation proximately caused by the use of separate bit line and separate sense amplifi...	06/05/1990
4837743	Architecture for memory multiplexing A solid state memory system is arranged in a plurality of blocks of memory cells, the memory cells in each block arranged in columns and rows. When the memory system is addressed for a memory reference, block selection circuitry selects one block of the p...	06/06/1989
4825410	Sense amplifier control circuit An improved memory sensing control circuit is provided wherein pulses derived from row or word address changes and from column or bit address changes are used to produce set pulses which are applied at optimum time intervals to a sense amplifier. More par...	04/25/1989
4811298	Decoding circuit arrangement for redundant semiconductor storage systems A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well a...	03/07/1989
4750839	Semiconductor memory with static column decode and page mode addressing capability A semiconductor memory includes a memory array (10) that is operable to be addressed in either the page mode or the static column decode mode. A column address transparent latch (20) is provided which is controlled to either directly input a column addres...	06/14/1988
4706222	Darlington type switching stage for a line decoder of a memory A switching stage receives two levels at its input, i.e. a high selection level and a low non-selection level. The Darlington stage (T1, T2) supplies at its output (E) a high current in the selected mode and a considerably smaller cu...	11/10/1987
4635234	Memory circuit with an improved output control circuit A memory circuit of the type having a plurality of output circuits whose peak currents can be reduced. A plurality of timing signals are generated at different time points, and applied to sequentially enable the plurality of output circuits....	01/06/1987

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Class 365/241 - Detectors