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| Number | Title | Issue Date |
| 7733739 | Synchronous semiconductor memory device A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the col... | 06/08/2010 |
| 7525871 | Semiconductor integrated circuit Fuse data is supplied to each of a plurality of function blocks through a transfer path using shift registers. When the reliability of fuse elements is low, there is a possibility that a part of the fuse data may have an error. Further, when the transfer path of the... | 04/28/2009 |
| 7433246 | Flash memory device capable of storing multi-bit data and single-big data There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bi... | 10/07/2008 |
| 7426153 | Clock-independent mode register setting methods and apparatuses Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write ... | 09/16/2008 |
| 7366031 | Memory arrangement and method for addressing a memory A memory arrangement includes a plurality of switching elements arranged in the form of a binary tree. The memory elements are supplied with data to be stored by the switching elements coupled to the leaves of the binary tree. ... | 04/29/2008 |
| 7355917 | Two-dimensional data memory A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjac... | 04/08/2008 |
| 7353418 | Method and apparatus for updating serial devices The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the ... | 04/01/2008 |
| 7345949 | Synchronous semiconductor memory device A synchronous semiconductor memory device of the present invention includes: an operation controller for outputting a column active sense pulse in response to a column address and a column command signal; a shift register controller, activated in response to the col... | 03/18/2008 |
| 7330378 | Inputting and outputting operating parameters for an integrated semiconductor memory device An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the regi... | 02/12/2008 |
| 7315479 | Redundant memory incorporating serially-connected relief information storage A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in seri... | 01/01/2008 |
| 7310262 | Ferroelectric memory capable of continuously fast transferring data words in a pipeline A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling ... | 12/18/2007 |
| 7307913 | Clock control device for toggling an internal clock of a synchronous DRAM for reduced power consumption A clock control device includes a set circuit for triggering an input address in response to an internal command signal to output a first address, a shift register including a plurality of flip-flops connected in series wherein some of the flip-flops perform a flip-... | 12/11/2007 |
| 7304906 | Method of controlling mode register set operation in memory device and circuit thereof Disclosed is a method of controlling an MRS operation in a memory device which can prevent an unnecessary MRS operation due to a malfunction of the memory device at a time when the memory device exits from a self-refresh mode. According to this method, external addr... | 12/04/2007 |
| 7305058 | Multi-standard clock rate matching circuitry Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control ... | 12/04/2007 |
| 7277351 | Programmable logic device memory elements with elevated power supply levels Programmable logic device integrated circuits are provided. The programmable logic device integrated circuits contain programmable core logic powered at a programmable core logic power supply voltage. Programmable logic device configuration data is loaded into the m... | 10/02/2007 |
| 7231511 | Microinstruction pointer stack including speculative pointers for out-of-order execution Methods and apparatus, including computer program products, for a microinstruction pointer stack in a processor. A method executed in a processor includes executing microcode (μcode) addressed by pointers stored in an out-of-order microinstruction pointer (μIP) st... | 06/12/2007 |
| 7227812 | Write address synchronization useful for a DDR prefetch SDRAM Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to ... | 06/05/2007 |
| 7227777 | Mode selection in a flash memory device A single flash memory device has selectable read modes for either a segment mode or a page mode. The desired mode is selected by writing a control word to a mode control register. Selecting the segment mode causes the device to output selected memory segments. Selec... | 06/05/2007 |
| 7216215 | Data access method applicable to various platforms A data access method uses variable mask data and shift amount to write data into or read data from a data storage zone. The mask data and shift amount are determined according to starting and end data bit addresses in a bit range of the data to be read or written. T... | 05/08/2007 |
| 7205792 | Methods and circuitry for implementing first-in first-out structure Methods and circuitry for implementing high speed first-in first-out (FIFO) structures. In one embodiment, a FIFO is disclosed that allows the frequency of one clock, e.g., the write clock, to be different than (e.g., half) that of the other (read) clock. In another... | 04/17/2007 |
| 7203109 | Device and method for detecting corruption of digital hardware configuration A device for verifying hardware in a circuit arrangement that includes one or more configuration elements (106) operable to configure hardware elements (108) that are electrically coupled by one or more electrically-conductive pathways (110). Th... | 04/10/2007 |
| 7187604 | Semiconductor memory A shift register includes plural latches corresponding to normal word lines of normal memory cell rows and a redundancy word line of a redundancy memory cell row, respectively, in order to sequentially activate any of the redundancy word line and the normal word lin... | 03/06/2007 |
| 7180797 | Reduced power registered memory module and method A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip selec... | 02/20/2007 |
| 7177225 | Block redundancy implementation in heirarchical RAM'S The present invention relates to a system and method for providing redundancy in a hierarchically memory, by replacing small blocks in such memory. The present invention provides such redundancy (i.e., replaces such small blocks) by either shifting predecoded lines ... | 02/13/2007 |
| 7148826 | Data input circuit and semiconductor device utilizing data input circuit A data input circuit converts input serial data to n-bit parallel data, and outputs the n-bit parallel data by following an address signal. The data input circuit includes a data shifting unit including a plurality of columns, and sequentially shifting the input ser... | 12/12/2006 |
| 7145832 | Fully-hidden refresh dynamic random access memory A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the ... | 12/05/2006 |
| 7116578 | Non-volatile memory device and data storing method In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a ... | 10/03/2006 |
| 7107393 | Systems and method for transferring data asynchronously between clock domains An asynchronous FIFO buffer communicates data between an input clock domain and a relatively slow output clock domain. The input clock frequency is not an even multiple of the output clock frequency, so the data transfer is asynchronous. The FIFO buffer includes a c... | 09/12/2006 |
| 7076600 | Dual purpose interface using refresh cycle A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal pat... | 07/11/2006 |
| 7072231 | Reduced power registered memory module and method A registered memory module includes a plurality of flip-flops having respective data terminals, respective clock terminals receiving a clock signal and output terminals coupled to a plurality of SDRAM devices in the module. A logic gate decodes respective chip selec... | 07/04/2006 |
| 7068280 | Method and apparatus to provide overlay buffering Overlay buffering scheme for multi-channel data in which one memory buffer content is overlayed over another as memory locations of an input buffer are freed when data is output from the input buffer. By overlaying the buffer content, only one input buffer is used, ... | 06/27/2006 |
| 7061827 | Semiconductor memory device A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is c... | 06/13/2006 |
| 7061783 | Content addressable memory (CAM) capable of finding errors in a CAM cell array and a method thereof A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing uni... | 06/13/2006 |
| 7061828 | Fully-hidden refresh dynamic random access memory A composite gate detects whether an internal array is in a selected state and an internal row activation signal is activated in accordance with a timing relationship between an output signal of the composite gate and an address transition detection signal. When the ... | 06/13/2006 |
| 7061821 | Address wrap function for addressable memory devices The invention is a selectable function that permits the address portion of data words to be separated from the storable content portion and that address portion to be used for different purposes without disturbing the stored contents in the memory array. The inventi... | 06/13/2006 |
| 7057946 | Semiconductor integrated circuit having latching means capable of scanning Circuits have a certain function. A plurality of first registers are connected in series, and shift stored data to respective adjacent registers in sequence. A plurality of second registers are connected in series, and shift stored data to respective adjacent regist... | 06/06/2006 |
| 7054222 | Write address synchronization useful for a DDR prefetch SDRAM Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to ... | 05/30/2006 |
| 7054218 | Serial memory address decoding scheme A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of ... | 05/30/2006 |
| 7035983 | System and method for facilitating communication across an asynchronous clock boundary A method includes storing data in one of a plurality of memory slots in a queue. Each memory slot is associated with a plurality of flags. The method also includes toggling a first of the flags associated with the slot. The method further includes retrieving the dat... | 04/25/2006 |
| 7027348 | Power efficient read circuit for a serial output memory device and method An integrated circuit memory device has a plurality of memory cells arranged in a plurality of arrays. Each array has a plurality of rows, and a plurality of column lines, and a plurality of row lines connecting to the memory cells in each array. The memory cell in ... | 04/11/2006 |
