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| Number | Title | Issue Date |
| 5384744 | Look ahead flag for FIFO The invention provides fast generation of flag signals for devices such as a first-in first-out buffers by looking ahead and predetermining flag signals for future possible states of the device. Predetermining flag signals does not delay flag output becau... | 01/24/1995 |
| 5381367 | Semiconductor memory device and an operating method of the same First and second input/output line groups are provided. A plurality of first bit line groups are connected to the first input/output line group through corresponding column selecting circuits, respectively. A plurality of second bit line groups are connec... | 01/10/1995 |
| 5374851 | Memory apparatus In a memory device, data stored in memory cells bridging memory cell columns for two lines can be read out in response to an address signal supplied only once. The memory cells (R00-R03), (R10-R13), (R10-R13), (R20-R23)m (R20-R23) and (R30-R33) for the tw... | 12/20/1994 |
| 5371714 | Method and apparatus for driving word line in block access memory In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timin... | 12/06/1994 |
| 5371708 | FIFO-type semiconductor device A semiconductor memory device of FIFO type is disclosed. The memory device has a test function for easy analysis of irregularities. A read data register for holding read data from the memory cells and a write data register for holding write data to the ce... | 12/06/1994 |
| 5367495 | Random access memory having control circuit for maintaining activation of sense amplifier even after non-selection of word line A MOS memory device operating at high speed which is so constructed as to hold the sense amplifier activating signals SAP and SAN at high potential and at low potential, respectively, even after the completion of a memory access, and keep the sense amplif... | 11/22/1994 |
| 5365485 | Fifo with fast retransmit mode A clocked first-in first-out (FIFO) memory includes interleaved dual-port static random access memories (SRAM's) 32 and 36. The FIFO has status flags 44 to indicate empty and full conditions and two programmable flags, almost full and almost empty, to ind... | 11/15/1994 |
| 5363337 | Integrated circuit memory with variable addressing of memory cells An integrated circuit memory array has a data input/output, a Read/Write* signal input, a row decoder, and a column decoder. An input circuit inputs a beginning and ending address to an on-chip memory controller which then sequentially addresses the begin... | 11/08/1994 |
| 5343426 | Data formater/converter for use with solid-state disk memory using storage devices with defects A computer system includes a main memory that is able to make use of DRAM memory devices having a relatively high level of bad cells (hard faults). An EDC circuit is provided which uses combinatorial logic to perform a BCH code type of error detection and... | 08/30/1994 |
| 5343435 | Use of a data register to effectively increase the efficiency of an on-chip write buffer Using a separate data register effectively increases the efficiency of an on-chip write buffer implemented as a FIFO structure. The separate register holds the output data during write cycles, allowing the write buffer FIFO to make the space consumed by t... | 08/30/1994 |
| 5331598 | Memory control device A memory control device for controlling writing and reading data in and from a line memory made up of a plurality of FIFO memories. Writing clocks are circularly applied to the plurality of FIFO memories of the line memory. Also, reading clocks are circul... | 07/19/1994 |
| 5329493 | Integrated semiconductor memory array and method for operating the same An integrated semiconductor memory array includes a memory region, a writing buffer memory associated with the memory region, a writing pointer and an input buffer associated with the writing buffer memory, a reading buffer memory associated with the memo... | 07/12/1994 |
| 5305257 | Semiconductor integrated circuit A semiconductor integrated circuit includes "n" cascaded inverters IVj ("j"="1" to "n") formed of MOS transistors. The size of an input side MOS transistor and the size of an output side MOS transistor of each inverter are determined so that an... | 04/19/1994 |
| 5305281 | Multiple array memory device with staggered read/write for high speed data access A multiple array memory device formed on a single IC chip performing transfers of a series of data between the device and its interface at high speed. The device includes a memory having a plurality of groups of memory arrays. In a read operation, the dev... | 04/19/1994 |
| 5297086 | Method for initializing redundant circuitry A method for initilizing redundant circuitry of a semiconductor memory device is disclosed. The method comprises sectioning the redundant circuitry and applying an initilizing pulse to each section of redundant circuitry at a different time during power u... | 03/22/1994 |
| 5293332 | Semiconductor memory device with switchable sense amps A semiconductor memory device, in which based on a write and non-write states of a memory transistor, a signal corresponding to a page mode and a normal mode is generated, and a switch circuit activates all sense amplifiers corresponding to memory array b... | 03/08/1994 |
| 5291457 | Sequentially accessible non-volatile circuit for storing data A sequentially accessible, non-volatile data storage circuit for generating constants includes a logic array for non-volatile storage of programmed data words and a recirculating shift register for causing the first one of the data words to appear at a da... | 03/01/1994 |
| 5287324 | Multiport DRAM A multiport DRAM having a DRAM cell array; a sequential access memory (SAM) for inputting data of a specific length to the DRAM cell array and transmitting that data to an external device; a SAM address counter for counting the addresses of the data in th... | 02/15/1994 |
| 5274602 | Large capacity solid-state memory A large capacity, solid-state memory device is disclosed in which information is stored in a plurality of large-area arrays of memory cells, each of which is a crossed-wire matrix of memory cells fabricated in a continuous process on a thin flexible subst... | 12/28/1993 |
| 5272678 | Semiconductor memory device with column-wise signal access A semiconductor memory device according to the present invention has data reading lines provided corresponding to word lines, second switches disposed between memory cells and the data reading lines to deliver data onto the data reading lines in accordanc... | 12/21/1993 |
| 5267200 | Semiconductor memory device and operating method thereof with transfer transistor used as a holding means A semiconductor memory device comprises a memory cell array (1) comprising a plurality of memory cells (MC) arranged in a matrix. A Y decoder (5) is responsive to an external address signal for outputting a selecting signal which simultaneously selects a ... | 11/30/1993 |
| 5257237 | SAM data selection on dual-ported DRAM devices The selection in a dual port memory device of data from a serial access memory register having a lower byte and an upper byte of data is described herein. In one embodiment, the register is partitioned lengthwise into two sections, corresponding to, for e... | 10/26/1993 |
| 5255220 | Dual port video memory system having pulse triggered dual column addressing Read column conductors and write column conductors of a memory array are addressed by respective triggerable sequential pulse generators which, upon receiving respective trigger pulses, provide respective read and write address pulses to respective column... | 10/19/1993 |
| 5255242 | Sequential memory A sequential memory (10) uses interleaved memories (12a-b) with associated output buffers (22a-b) accomplish high data rates. Data access control circuitry (18) and bank select circuitry (20) control the order in which the memory banks (12a-b) are written... | 10/19/1993 |
| 5253213 | Semiconductor memory used for changing sequence of data An SRAM adapted for changing the sequence of data. A counter 7 generates a sequentially increasing address signal. A write designation circuit 2a sequentially designates a memory cell row to be selected for writing in response to the address signal. Conve... | 10/12/1993 |
| 5250857 | Dynamic logic circuit with reduced operating current In a dynamic logic circuit, an X decoder and a Y decoder receive a more significant bit portion and a less significant bit portion of an internal address generated by a sequencer, respectively. A precharge signal supplied to the X decoder is generated whe... | 10/05/1993 |
| 5247484 | Multiport DRAM A plurality of RAM blocks constituting a first RAM section and a second RAM section, respectively are arranged alternately in such a way that the inversion bit lines and the non-inversion bit lines of these RAM blocks are changed alternately block by bloc... | 09/21/1993 |
| 5237532 | Serially-accessed type memory device for providing an interleaved data read operation In a semiconductor memory having a column-direction serial access function, two systems of circuits for selecting and fetching data are provided. A circuit operation is alternately performed such that one system is set up while the other system is accesse... | 08/17/1993 |
| 5222047 | Method and apparatus for driving word line in block access memory In a block access memory in which the memory cell array is divided into a plurality of blocks and data input/output is carried out by block unit, each block is divided into a plurality of subblocks, and the timing of activating the word line and the timin... | 06/22/1993 |
| 5208775 | Dual-port memory device If a defect is occurred in a certain normal memory when a dual-port memory device having a first and a second normal memory carries out the data transfer by a first and a second transfer signal, either of the first or the second transfer signals which cor... | 05/04/1993 |
| 5206834 | Semiconductor memory device performing last in-first out operation and the method for controlling the same A LIFO device includes a plurality of memory circuits (1), a write address pointer (2) and a read-out address pointer (3). The write address pointer (2) selects the memory circuit (1) in which data are to be written, while the read-out address pointer (3)... | 04/27/1993 |
| 5202857 | System for generating memory timing and reducing memory access time A system for generating memory timing signals and for reducing memory access time includes a plurality of memory modules having an array of memory cells addressable in response to a number of row address select and column address select signals. A row add... | 04/13/1993 |
| 5200925 | Serial access semiconductor memory device and operating method therefor A serially accessible memory device includes a plurality of memory cell array blocks, a plurality of input buffers each separately provided for each cell array block for receiving different data in a data stream, a plurality of output buffers each separat... | 04/06/1993 |
| 5157633 | FIFO memory device An FIFO memory device which is used for digital communication devices and the like comprises a plurality of D-flip flops cascade-connected with each other for storing data; selectors connected between the D-flip flops for selecting an input data or a data... | 10/20/1992 |
| 5155705 | Semiconductor memory device having flash write function A semiconductor memory device with a flash write function includes word lines and bit lines; memory cells connected between the word lines and the bit lines; and a flash write mode designating unit for designating a flash write mode in accordance with ext... | 10/13/1992 |
| 5151983 | Microcomputer system with selectively bypassed memory output latches A microcomputer system includes a memory storing various processing data including instruction codes, and a data processor for executing an instruction. The memory includes an address pointer for indicating an address for the memory and supplying the stor... | 09/29/1992 |
| 5136588 | Interleaving method and apparatus An interleaving method and apparatus suitable for burst error correction occurring in data transmission or reading of recording medium. In the interleaving method in which data to be transmitted is once written in a storing means and then read to be outpu... | 08/04/1992 |
| 5097447 | Semiconductor memory device having a serial access memory A semiconductor memory device includes a RAM and a serial access memory (SAM). The SAM includes an address counter which generates a slave address and a master address. The slave address precedes the master address by half the period of a serial access st... | 03/17/1992 |
| 5072424 | Wafer-scale integrated circuit memory A wafer scale integrated circuit comprises a few hundred modules (10) which can be connected into a long chain by commands sent to the modules along a transmit path set up by way of module inputs (XINN, XINE, XINS, XINW) from neighboring modules and outpu... | 12/10/1991 |
| 5065368 | Video RAM double buffer select control An implementation of a serial access memory register that facilitates the selecting from two alternate frame buffers on a per pixel basis. The frame buffers are each stored in a portion of a row in a single video RAM. Following data transfer to the serial... | 11/12/1991 |
