Did You Know...
...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 4485461 | Memory circuit A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits ... | 11/27/1984 |
| 4475181 | Semiconductor memory A semiconductor memory of multiplexed address inputs is made operative to receive column addresses and row addresses through common external address lines and to decode them consecutively in response to first and second strobe signals thereby to select on... | 10/02/1984 |
| 4458357 | Circuit board identity generator A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification... | 07/03/1984 |
| 4438512 | Method and apparatus for verifying storage apparatus addressing In a data storage system employing sequential data transfers for blocks of data bytes, an address offset is induced in the addressing mechanism such that each block transfer requires loading the address mechanism with an address of a block to be accessed.... | 03/20/1984 |
| 4409675 | Address gate for memories to protect stored data, and to simplify memory testing, and method of use thereof An address gate for a random access memory includes a pair of emitter-coupled and collector-coupled transistors, and another transistor emitter-coupled to the pair of transistors. Complimentary outputs are read at the coupled emitters of the pair of trans... | 10/11/1983 |
| 4344156 | High speed data transfer for a semiconductor memory A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locat... | 08/10/1982 |
| 4340943 | Memory device utilizing MOS FETs A memory device utilizing metal oxide semiconductor field effect transistors (MOS FETs) formed in a semiconductor substrate. The memory device is so improved as to be accessed without a delay and as not to behave erroneously, in spite of a potential varia... | 07/20/1982 |
| 4280199 | Apparatus for scanning an addressable memory Apparatus for scanning an addressable memory includes a clock pulse generator and an address counter for counting the clock pulses so as to produce an address for the addressable memory and thereby designate a corresponding storage location from which sto... | 07/21/1981 |
| 4231110 | Memory array with sequential row and column addressing An electronic memory comprises a plurality of memory cells arranged in an array of rows and column, row address circuitry, column address circuitry, circuitry for sensing the logic states of the cells, and circuitry for delaying addressing of a selected c... | 10/28/1980 |
| 4225948 | Serial access memory device A serial access memory device is disclosed which comprises a random access memory and a synchronous address counter. The address counter is arranged for generating successive address codes which differ by only one bit from each other. The write-enable inp... | 09/30/1980 |
| 4222102 | Data buffer memory of the "first-in, first-out" type, comprising a variable input and a variable output A data buffer memory of the "first-in, first-out" type, having an input bus by which data are applied to the buffer and an output bus by which data are taken up from the buffer. The buffer includes logic means whereby a variable input location and a varia... | 09/09/1980 |
| 4156938 | MOSFET Memory chip with single decoder and bi-level interconnect lines A dynamic random access read/write memory having 4,096 binary storage cells is disclosed. The system utilizes a single set of six address input buffers and one decoder for both row and column address information. The memory array includes two 32×64 array... | 05/29/1979 |
| 4153951 | Event marker having extremely small bit storage requirements A plurality of random access memories (RAMS) are each addressed by a binary sub-number, all sub-numbers making up a composite binary address number, the maximum count of which defines the total number of subintervals within a given pulse repetition interv... | 05/08/1979 |
| 4152781 | Multiplexed and interlaced charge-coupled serial-parallel-serial memory device An interlaced charge-coupled serial-parallel-serial memory device unscrambles the scrambled bit sequence produced by conventional interlacing, so that the output serial data bit stream has the same original bit sequency as the input bit stream.... | 05/01/1979 |
| 4092665 | Method and means for extracting variable length data from fixed length bytes Address codes are serially applied to parallel word-oriented memory banks, such as read-only memories, to read out successive sets of fixed length data words and control words in parallel. The data words contain variable length data, and the control words... | 05/30/1978 |
| 4060795 | Scanning system A scanning system is disclosed in which a multiplicity of points arranged in matrix are scanned column by column in accordance with the commands issued from a central controller, which scanning system comprises a memory and a scanning controller for scann... | 11/29/1977 |
| 4041482 | Character generator for the reproduction of characters In an apparatus which supplies characters or symbols and which is intended for service in different countries, some characters or symbols must have different forms for different countries or groups of countries. In the case of read-out apparatus which rep... | 08/09/1977 |
| 3991408 | Self-sequencing memory A self-sequenced read only memory is shown wherein each word line contains dynamic logic circuits for energizing a next word line after the fixed time delay provided by the dynamic logic circuits. Self-sequencing inverters are physically placed within the... | 11/09/1976 |
| 3962689 | Memory control circuitry A control circuit for reading from, and writing into, a random access memory into which successive data entries are stored at addresses in sequential binary order. A scan generator provides a repeated sequence of all sequential binary order addresses to t... | 06/08/1976 |
