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| Number | Title | Issue Date |
| 7907473 | Semiconductor memory device and data storage method including address conversion circuit to convert coordinate information of data into one-dimensional information to amplifier A semiconductor memory device for storing data defining a multidimensional space based on coordinate information of the data, includes: a cell array having memory cells arranged in a lattice pattern, for storing the data; a word line selector selecting and driving a... | 03/15/2011 |
| 7313639 | Memory system and device with serialized data transfer A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial... | 12/25/2007 |
| 7237048 | Memory system and device with serialized data transfer A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial... | 06/26/2007 |
| 7129938 | Low power circuits for active matrix emissive displays and methods of operating the same The embodiments of the present invention provide a flat panel display having a plurality of pixels, each comprising a light-emitting device configured to emit light in accordance with a current flowing through the light-emitting device, a transistor coupled to the l... | 10/31/2006 |
| 7111110 | Versatile RAM for programmable logic device Circuits and methods for providing versatile RAM for a programmable logic device are provided. These circuits and methods preferably allow signal lines that may be used to provide inputs for logic elements to be used instead for addressing memory blocks that form th... | 09/19/2006 |
| 7085159 | Highly compact non-volatile memory and method therefor with internal serial buses A non-volatile memory device capable of reading and writing a large number of memory cells with multiple read/write circuits in parallel has an architecture that reduces redundancy in the multiple read/write circuits to a minimum. The multiple read/write circuits ar... | 08/01/2006 |
| 7061480 | Image display A display cell includes a light sensor, a display element coupled to light sensor; and a memory coupled to the light sensor. A display and an optically addressable display system using a display cell are provided. Methods for using a display cell are also provided. | 06/13/2006 |
| 7016346 | Apparatus and method for converting data in serial format to parallel format and vice versa Converters and a corresponding method for converting serial data to parallel format and vice versa, particularly for use in switches for telecommunications applications. The converters comprise a storage element associated with each serial channel and comprising two... | 03/21/2006 |
| 6963499 | Static RAM with flash-clear function A memory cell comprises a first and a second inverters connected in a latch configuration. The inverters have respective first and second means for receiving a first and a second voltage supplies, respectively. The cell also comprises means, responsive to a memory c... | 11/08/2005 |
| 6910096 | SDRAM with command decoder coupled to address registers A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20... | 06/21/2005 |
| 6754135 | Reduced latency wide-I/O burst architecture A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base ... | 06/22/2004 |
| 6392947 | Semiconductor memory device To efficiently access pixel data stored in memory in the X direction and Y direction when carrying out error correction processing. In a data output section 10, a pixel block consisting the desired 2×2 pixel data W1-W4 is selected by inputting a address,... | 05/21/2002 |
| 6094375 | Integrated circuit memory devices having multiple data rate mode capability and methods of operating same Integrated circuit memory devices which are operable in both single and dual data rate modes (depending on the value of a mode select signal), include first and second memory cell arrays and first and second global input/output signal lines (GIOF, GIOS) e... | 07/25/2000 |
| 6052312 | Multiple-port ring buffer A computer graphics subsystem according to a preferred embodiment of the present invention has a video digital signal processor (VDSP) that normally requires a plurality of discrete field and line memories, but, instead, is adapted to use multiple-port ri... | 04/18/2000 |
| 5805524 | Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-arra... | 09/08/1998 |
| 5732011 | Digital system having high speed buffering A FIFO memory eliminates the delay associated with selecting memory locations during a read and write operation and prevents data intended to be saved from changing during the write operation. The FIFO memory includes a shift register having a plurality o... | 03/24/1998 |
| 5680127 | Parallel-to-serial conversion device and linear transformation device making use thereof A parallel-to-serial conversion device capable of improved space efficiency has a corner turn memory array provided in an input section of the device to perform parallel-to-serial conversion by writing in the row direction of the input section and by read... | 10/21/1997 |
| 5515329 | Variable-size first in first out memory with data manipulation capabilities A FIFO memory system exhibits data processing capabilities by the inclusion therein of a digital signal processor and an associated dynamic random access memory. The digital signal processor provides significant data processing on the fly while the dynami... | 05/07/1996 |
| 5497353 | Semiconductor memory device A multiport memory is provided which permits both random access and serial access. In order to reduce parasitic capacitance and improve operating speed, the serial input/output lines are each divided into two parts at their middle points. Sense amplifiers... | 03/05/1996 |
| 5473577 | Serial memory In a serial memory which internally converts serial input data into parallel data and writes the data into a memory array two or more bits at a time, and which reads data two or more bits at a time from the memory array and internally converts the read da... | 12/05/1995 |
| 5440518 | Non-volatile memory circuits, architecture and methods The invention enables random read and write operations into cells in an array that contains staggered source or drain connections from the memory cells in a given column. The invention comprises only one row decoder providing the required voltages to the ... | 08/08/1995 |
| 5317540 | Semiconductor memory device A semiconductor memory device comprises a memory cell array in which cascade-gate dynamic memory cells are arranged in a matrix and which contains word lines connected in common to the memory cells in the same row and bit lines connected in common to the ... | 05/31/1994 |
| 5313438 | Delay apparatus A delay apparatus comprises one or a plurality of shift registers, a plurality of signal accumulating capacitors which are mutually coupled by transfer transistors, a plurality of write switches each of which is arranged between an input terminal and eith... | 05/17/1994 |
| 5303200 | N-dimensional multi-port memory A three dimensional memory enabling both pixel and bit slice data to be stored and retrieved through different ports. A memory circuit (30) is divided into a lower memory block (32a) and an upper memory block (32b). Each memory block is organized into 256... | 04/12/1994 |
| 5168463 | Shift register apparatus for storing data therein An apparatus for storing digital data includes a clock pulse source and plural serial shift register stages storing data bits. Digital data signals, each having plural databits, are coupled to and shifted in the stages in synchronization with the clock pu... | 12/01/1992 |
| 5126808 | Flash EEPROM array with paged erase architecture A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel arc... | 06/30/1992 |
| 5111436 | 2D charge coupled device memory with acoustic charge transport multiplexer Two dimensional charge coupled device (CCD) memories are coupled to acoustic charge transport devices (ACT) which act as input and/or output multiplexers for the memories. In a preferred embodiment of the invention, the input to a NXM memory is in the for... | 05/05/1992 |
| 5095446 | Circuit for and method of controlling output buffer memory Data to be sent to a frame buffer memory keeping output data in a bit map form is subdivided into square blocks. The words arranged in the row direction are rotated in a column direction by a bit each time the row address is increased. The rotation amount... | 03/10/1992 |
| 5027322 | Circuit configuration for identification of integrated semiconductor circuitries A circuit configuration for the identification of integrated semiconductor circuitries includes n programmable elements. A common line is connected to the programmable elements. An n-stage serial-parallel shift register has a data input, n parallel output... | 06/25/1991 |
| 4992982 | SPS type charge coupled device memory suitable for processing video information with increased speed An SPS charge coupled device memory is described which is useful for storing video pictures. The memory avoids accumulation of charge below the de-interlacing electrodes controlling the transfer of data to the series output register by using two different... | 02/12/1991 |
| 4975880 | Memory system for storing data from variable numbers of input data streams The present invention constitutes a memory system comprising a multiple number of individual memory units (40-47) for storing digital data from a variable number of data input streams and for efficiently using the memory capacities of the memory units in ... | 12/04/1990 |
| 4947380 | Multi-mode memory device The invention relates to a memory device of the charge-coupled shift register type which is subdivided into four sections each of which has a storage capacity of, for example 208,800 bits and which can operate in different modes: parallel-in/parallel-out ... | 08/07/1990 |
| 4901286 | Digital FIFO memory A digital FIFO memory is disclosed which is formed by a memory cell array (zf) comprising of n signal channels (b1 . . . bn) each containing m memory cells (c..1, c..2, c..m-1, c..m) are first, second, and mth clock drivers (tt1, tt2, ttm-1, ttm), respect... | 02/13/1990 |
| 4888698 | Method for storing a parcelwise divided digital data base as well as of addressing a data parcel in a mass memory, and apparatus for carrying out the method A database is stored in a mass memory. For this purpose, it is first divided into main cells and then into base cells according to a predetermined regular division pattern. Each base cell is then checked to see whether its data content is sufficient to oc... | 12/19/1989 |
| 4875196 | Method of operating data buffer apparatus An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memo... | 10/17/1989 |
| 4845678 | Memory comprising simultaneously addressable memory elements A random access memory (1) is described in which one address of a row of addresses is activatable. There is also realized a block addressing mode in which all addresses between a selectable first address and a selectable second address are activated. To t... | 07/04/1989 |
| 4802136 | Data delay/memory circuit A data delay/memory circuit includes clock-controlled data latch circuits formed with cascade-connected clocked inverters. The data delay/memory circuit also includes a clock generator for supplying the clocked inverters with clock signals. These clock si... | 01/31/1989 |
| 4802125 | Memory access control apparatus A memory access control apparatus has a plurality of request reception sections, respectively connected to a plurality of units for supplying requests, for receiving a block read request from the corresponding units, and dividing the block read request in... | 01/31/1989 |
| 4799199 | Bus master having burst transfer mode A data processing system having a bus master and a memory which is capable of transferring operands in bursts of m in response to a burst request signal provided by the bus master, the operands being clustered modulo m about a selected access address prov... | 01/17/1989 |
| 4777624 | Dynamic memory device A dynamic memory device comprises a dynamic memory circuit, an input buffer circuit for temporarily storing data each time it is received from a source external to the device; an output buffer circuit for temporarily storing data each time it is read out ... | 10/11/1988 |
