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| Number | Title | Issue Date |
| 8120990 | Flexible memory operations in NAND flash devices A flash memory device having at least two bank, where the each bank has an independently configurable page size and core controller. The core controller is local to each bank, and governs memory access operations for the bank that include read, program and erase ope... | 02/21/2012 |
| 8120989 | Concurrent multiple-dimension word-addressable memory architecture An N-dimension addressable memory. The memory includes an N-dimension array of bit cells and logic configured to address each bit cell using N-Dimension Addressing (NDA), where N is at least two and the array of bit cells is addressable by N orthogonal address space... | 02/21/2012 |
| 8045416 | Method and memory device providing reduced quantity of interconnections Methods, devices and systems for reducing the quantity of external interconnections of a memory device are disclosed. Implementation of one such method, device and system includes inputting over an address bus a first portion of an address of a next row of memory ce... | 10/25/2011 |
| 7885141 | Non-volatile memory device and method for setting configuration information thereof Provided are a nonvolatile memory device and a method for setting configuration information of the nonvolatile memory device. The nonvolatile memory device can include a nonvolatile memory cell array, a configuration register and a configuration controller. The conf... | 02/08/2011 |
| 7729200 | Memory device, memory controller and memory system The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the pag... | 06/01/2010 |
| 7668040 | Memory device, memory controller and memory system The memory device has: a plurality of banks, each of which has a memory cell array having a plurality of page areas that are selected by row addresses respectively, and each of which is selected by a bank address; a row controller that controls activation of the pag... | 02/23/2010 |
| 7606111 | Synchronous page-mode phase-change memory with ECC and RAM cache Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on t... | 10/20/2009 |
| 7590027 | Nonvolatile semiconductor memory device A nonvolatile semiconductor device includes a plurality of word lines, a plurality of bit lines, a plurality of memory cell arrays having a plurality of electrically reprogrammable memory cells which are connected to said word lines and said bit lines, a data progra... | 09/15/2009 |
| 7577059 | Decoding control with address transition detection in page erase function Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of ea... | 08/18/2009 |
| 7535792 | Data transmission control device, and data transmission control method A data transmission control device includes: a memory control unit that is connected to a DRAM, and accesses to the DRAM in accordance with a read/write request from various devices that request read/write of data from/into the DRAM; and a command control unit that ... | 05/19/2009 |
| 7525870 | Methods for optimizing page selection in flash-memory devices The present invention discloses methods for storing data in a flash-memory storage device, the method including the steps of: receiving, by the device, primary data to be stored in the device and to be read from the device at a primary reading speed; storing at leas... | 04/28/2009 |
| 7505358 | Synchronous semiconductor memory device A synchronous semiconductor memory device can perform an internal operation for an input address with reliability regardless of the frequency of a system clock. The semiconductor memory device includes an internal operation detecting unit for generating a flag signa... | 03/17/2009 |
| 7440338 | Memory control circuit and memory control method A memory control circuit that controls m (=L/k) memories (first to mth memories), each of which has a k-bit width, the m memories storing data having a data width (D bits) of an integral multiple of k bits up to L bits, the circuit comprising: an address input circu... | 10/21/2008 |
| 7437501 | Combining the address-mapping and page-referencing steps in a memory controller A method and apparatus for parallelizing address-mapping and page referencing in a memory controller. The page referencing may apply an input address to two separate content addressable memory components along with masks from a configuration register identifying ran... | 10/14/2008 |
| 7433246 | Flash memory device capable of storing multi-bit data and single-big data There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bi... | 10/07/2008 |
| 7400549 | Memory block reallocation in a flash memory device A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coup... | 07/15/2008 |
| 7400534 | NAND flash memory and data programming method thereof A semiconductor integrated circuit device includes even-numbered bit lines, odd-numbered bit lines, cell source lines, first memory elements electrically connected between the even-numbered bit lines and the cell source lines, and second memory elements electrically... | 07/15/2008 |
| 7397727 | Write burst stop function in low power DDR sDRAM A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device,... | 07/08/2008 |
| 7391645 | Non-volatile memory and method with compensation for source line bias errors Source line bias is an error introduced by a non-zero resistance in the ground loop of the read/write circuits. During sensing the source of a memory cell is erroneously biased by a voltage drop across the resistance and results in errors in the applied control gate... | 06/24/2008 |
| 7385849 | Semiconductor integrated circuit device A semiconductor integrated circuit device is disclosed. The device includes a memory cell array, an I/O buffer, a read/write buffer, an error checking and correcting circuit, and an initialization checking circuit. N-bit data is input to the I/O buffer and the I/O b... | 06/10/2008 |
| 7379352 | Random access memory (RAM) method of operation and device for search engine systems A search engine system (100) is disclosed that can include at least one content addressable memory (CAM) device (102) arranged in a cascade configuration with at least one memory device (104), such as a static random access memory (SRAM). A CAM ... | 05/27/2008 |
| 7376041 | Semiconductor memory device and data read and write method of the same A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read contro... | 05/20/2008 |
| 7373575 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 05/13/2008 |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| 7369438 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that... | 05/06/2008 |
| 7366020 | Flash memory device capable of preventing an overerase of flash memory cells and erase method thereof We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string ... | 04/29/2008 |
| 7366037 | Semiconductor memory A semiconductor memory includes: first and second bit lines; a precharge circuit for precharging the first and second bit lines to a predetermined potential; a plurality of memory cells each connected to the first or second bit line, a selected one of the memory cel... | 04/29/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7363501 | Semiconductor integrated circuit with function to manage license information A semiconductor integrated circuit includes one or more function blocks, a nonvolatile memory unit which stores therein coded license information, and a decoder circuit which decodes the license information stored in the nonvolatile memory unit, and makes one of the... | 04/22/2008 |
| 7356620 | Apparatus and methods for communicating with programmable logic devices A circuit arrangement includes a programmable logic device. The programmable logic device includes configuration logic circuitry. The programmable logic device also includes configurable interconnects. The circuit arrangement further includes a storage device config... | 04/08/2008 |
| 7353401 | Device and method for data protection by scrambling address lines A device and method for data protection by scrambling address lines is disclosed, which includes a redundancy area-setting unit, a redundancy area-mapping rule unit, an area check unit, an address-mapping unit and a multiplexer. The area check unit compares an addre... | 04/01/2008 |
| 7352623 | NOR flash memory device with multi level cell and read method thereof A NOR flash memory device includes a multi level memory cell coupled to a bit line configured to be sensed in response to a word line voltage, and a discharge circuit configured to discharge the bit line when the multi level memory cell is sensed as an on cell. ... | 04/01/2008 |
| 7335937 | Nonvolatile semiconductor memory In an EEPROM consisting of a NAND cell in which a plurality of memory cells are connected in series, the control gate voltage Vread of the memory cell in a block selected by the data read operation is made different from the each of the voltages Vsg1... | 02/26/2008 |
| 7334080 | Nonvolatile memory with independent access capability to associated buffer A non-volatile storage device (1) has non-volatile memory units (FARY0 to FARY3), buffer units (BMRY0 to BMRY3) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer ... | 02/19/2008 |
| 7330368 | Three-dimensional semiconductor device provided with interchip interconnection selection means for electrically isolating interconnections other than selected interchip interconnections In a three-dimensional semiconductor device in which a plurality of semiconductor circuit chips are stacked and that is provided with a plurality of interchip interconnections for signal transmission between these semiconductor circuit chips, when transmitting signa... | 02/12/2008 |
| 7327604 | Clock synchronized non-volatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 02/05/2008 |
| 7324375 | Multi-bits storage memory A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 01/29/2008 |
| 7317654 | Non-volatile memory devices having multi-page programming capabilities and related methods of operating such devices Methods of programming a non-volatile memory device having at least one memory block with a plurality of memory cells located at intersections of rows and columns is disclosed. Pursuant to these methods, at least two addresses that select corresponding rows of the m... | 01/08/2008 |
| 7310262 | Ferroelectric memory capable of continuously fast transferring data words in a pipeline A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling ... | 12/18/2007 |
| 7298650 | Page buffer for a programmable memory device A page buffer is provided for an electrically programmable memory that includes multiple memory cells forming multiple memory pages. The page buffer includes a register for at least temporarily storing data read from or to be written to the memory cells of a selecte... | 11/20/2007 |
