Class 365/236 - Counting

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter wherein a memory location is addressed by
No. of patents: 753
Last issue date: 10/18/2011

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Number	Title	Issue Date
6563745	Memory device and method for dynamic bit inversion A memory device and method for storing bits in a memory array is provided. In one preferred embodiment, a memory device is provided comprising a plurality of memory cells that are in a first digital state and can be switched to a second digital state. A p...	05/13/2003
6560155	System and method for power saving memory refresh for dynamic random access memory devices after an extended interval A delay device is added to the addressing and refreshing circuitry of a DRAM array comprised of DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals...	05/06/2003
6556497	Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in t...	04/29/2003
6556489	Method and apparatus for determining digital delay line entry point A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a da...	04/29/2003
6552956	Semiconductor memory device and non-volatile semiconductor memory device provided with a plurality of internal counters A non-volatile semiconductor memory device 1 includes a first address counter 6 and a second address counter 8. The non-volatile semiconductor memory device 1 further includes two control counters, namely, a first control counter 2 and a second control co...	04/22/2003
6545932	SDRAM and method for data accesses of SDRAM An SRAM which eliminates any seam in consecutive read/write data flows when the burst-length is short, thus making it possible to achieve a seamless access in the burst-mode against data of different row-addresses between banks. This operation enables the...	04/08/2003
6545931	Semiconductor memory device with improved flexible redundancy scheme A spare memory array having spare memory cells common to a plurality of normal sub-arrays having a plurality of normal memory cells is provided. A spare line in the spare array can replace a defective line in the plurality of normal sub-array. The defecti...	04/08/2003
6542425	Refresh control circuit for controlling refresh cycles according to values stored in a register and related refreshing method A refresh control circuit is provided for controlling refresh cycles according to values stored in a register. A related refreshing method is also provided. The refresh control circuit controls the refresh cycles so as to refresh data stored in memory cel...	04/01/2003
6538938	Method for generating memory addresses for accessing memory-cell arrays in memory devices A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate me...	03/25/2003
6535457	Semiconductor memory device having clock generator for controlling memory and method of generating clock signal A semiconductor memory device having a clock generator for controlling a memory and a method of generating a clock are provided. The semiconductor memory device includes a processor, a program memory unit, and a clock generator. The processor generates co...	03/18/2003
6535456	Semiconductor memory device A semiconductor device includes a memory cell array, a counting section, a control section, a specification section and a data input/output section. The counting section configured to count transition of the clock signal and determine first data of a plur...	03/18/2003
6529426	Circuit and method for varying a period of an internal control signal during a test mode The invention is a dynamic random access memory (DRAM) device having an electronic test key fabricated on board and is a method for testing the DRAM. The electronic test key generates a signal which effects a variation in a period of an internal control s...	03/04/2003
6525988	Clock generating circuits controlling activation of a delay locked loop circuit on transition to a standby mode of a semiconductor memory device and methods for operating the same Clock generating circuits for a semiconductor memory device are provided. The clock generating circuits include a delay locked loop (DLL) circuit that generates an internal clock signal for the semiconductor memory device. A control circuit activates the ...	02/25/2003
6525981	Full page increment/decrement burst for DDR SDRAM/SGRAM A graphics subsystem having a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), which has a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a m...	02/25/2003
6510102	Method for generating memory addresses for accessing memory-cell arrays in memory devices A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate me...	01/21/2003
6510101	Clock-synchronous semiconductor memory device A semiconductor device includes a memory cell array, a control section and latency setting circuit. The control section configured to receive a clock signal and a first control signal, and configured to output a plurality of the data in synchronism with t...	01/21/2003
6504750	Resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled...	01/07/2003
6498746	Disturbing a ferroelectric memory array in a particular direction A method and apparatus for disturbing a ferroelectric memory array in a particular direction. The method counts a number of consecutive memory operations of a same type applied to the array and then determines if the number of consecutive memory operation...	12/24/2002
6496437	Method and apparatus for forcing idle cycles to enable refresh operations in a semiconductor memory A method is provided for operating a memory system having a plurality of memory blocks. The method includes (1) periodically asserting a timing signal; (2) asserting a refresh pending signal in each of the memory blocks when the asserted timing signal is ...	12/17/2002
6496423	Chip ID register configuration A chip ID register configuration includes a shift register having individual stages. A fuse device connected to the shift register has fuses each substantially assigned to a respective one of the individual stages of the shift register, for identifying a ...	12/17/2002
6490215	Semiconductor memory device and refreshing method of semiconductor memory device A semiconductor memory device that suppresses an increase in the circuit area which is originated from the layout of address signal lines. The semiconductor memory device includes refresh address counters, a switch circuit, and address holding circuits. T...	12/03/2002
6483773	Method for generating memory addresses for testing memory devices A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate me...	11/19/2002
6473864	Method and system for providing power management to a processing system A method and system for controlling a program in a processor system is disclosed. The processor system includes processor, a normal memory and a fast memory. The method and system comprises partitioning the program into a performance critical portion and ...	10/29/2002
6469932	Memory with row redundancy A flash memory device incorporating redundant rows. The memory device includes a memory array, control circuitry and a register. The control circuitry controls operations to the memory array. The register stores an address of a defect in the memory array ...	10/22/2002
6452868	Method for generating memory addresses for accessing memory-cell arrays in memory devices A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate me...	09/17/2002
6449214	Statistics counter overflow content addressable memory (CAM) and method A method and means to reduce memory requirements for storing statistics by recording, in a separate overflow memory, the most significant bits of counters requiring more bits than provided in the main statistics memory. A binary CAM provides the linking m...	09/10/2002
6449204	DYNAMIC SEMICONDUCTOR MEMORY DEVICE CAPABLE OF REARRANGING DATA STORAGE FROM A ONE BIT/ONE CELL SCHEME IN A NORMAL MODE TO A ONE BIT/TWO CELL SCHEME IN A TWIN-CELL MODE FOR LENGTHENING A REFRESH INTERVAL In a data holding mode, data storage in a one bit/one cell scheme in a normal operating mode are rearranged into data storage in a twin-cell mode in which data are stored in a one bit/two cell scheme. In the twin-cell mode, two sub word lines are simultan...	09/10/2002
6442096	Fast accessing of a memory device Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circu...	08/27/2002
6434062	Delay locked loop for use in semiconductor memory device It is provided a delay locked loop for obtaining a reduced jitter and a stable time delay adjustment to thereby perform a bi-directional time delay with a small area even at low frequency applications. The delay locked loop includes an input unit for rece...	08/13/2002
6430096	Method for testing a memory device with redundancy A method of accessing the memory elements in a packaged part, which has an internal address counter, N external lines for addressing a memory element, and (2N +M) addressable memory elements. The access method comprising a step of causing the p...	08/06/2002
6425103	Programmable moving inversion sequencer for memory bist address generation A low-complexity method and apparatus for generating address sequences for the moving inversion test method. In one embodiment, the address sequence generator includes a ring of counter cells in which each cell is configured to provide a toggle signal to ...	07/23/2002
6418078	Synchronous DRAM device having a control data buffer A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and outpu...	07/09/2002
6418065	Nonvolatile semiconductor memory Disclosed is a semiconductor memory having an internal booster, such as a flash memory, in which a situation that the program cannot escape from a writing operation can be avoided, and the writing operation can be promptly finished according to the level ...	07/09/2002
6404688	Semiconductor memory device having a self-refresh operation A semiconductor memory device having a self-refresh operation includes a first circuit generating a first signal that specifies a first self-refresh cycle by a non-volatile circuit element provided in the semiconductor memory device, a second circuit rece...	06/11/2002
6404687	Semiconductor integrated circuit having a self-refresh function A self-refresh circuit included in a semiconductor integrated circuit includes a ring oscillator, a double period counter, an SELF generating portion generating a signal SELF0 corresponding to an internal RAS, and a BBUE generating portion. The double per...	06/11/2002
6396747	Semiconductor memory device capable of high speed input/output of wide bandwidth data by improving usage efficiency of external data bus Serial write data of the burst length transmitted to a data bus are stored in parallel in latch circuits by a S/P data conversion circuit. In a memory cell array, one row of memory cells and four columns of memory cells are rendered active at the same tim...	05/28/2002
6388937	Semiconductor memory device A semiconductor memory device according to the present invention includes a burst counter for sequentially automatically generating an address of a predetermined bit number in synchronism with a clock on the basis of a predetermined sequence in the subseq...	05/14/2002
6388930	Method and apparatus for ram built-in self test (BIST) address generation using bit-wise masking of counters A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to...	05/14/2002
6385275	Assembly for generating a consecutive count An assembly for generating a consecutive count includes an n-stage binary counter (24) incrementable by counting pulses in successive cycles and an EEPROM (10) in which an item of information representing the count achieved in each case is stored in the p...	05/07/2002
6381195	Circuit, apparatus and method for generating address A circuit and a method for generating an address, which can generate a plurality of types of address on the basis of a reference address, and an apparatus for generating an address, which can generate the different addresses from one another by using a pl...	04/30/2002

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Class 365/236 - Counting