Did You Know...
...that the first rickshaw was invented in 1869 by an American Baptist minister, the Rev. E. Jonathan Scobie, to transport his invalid wife around the streets of Yokohama?
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6707699 | Historical information storage for integrated circuits The present invention describes an information recorder which is integrated into an IC, such as ferroelectric RAM device. The recorder counts desired events, such as memory accesses or length of time powered up and stores such information in a latch. The information... | 03/16/2004 |
| 6700809 | Entry relocation in a content addressable memory device Entry relocation in a content addressable memory (CAM) device. The CAM device is instructed to store a first value and to supply an address at which the first value is stored. If the address indicates that the first value has been stored within an overflo... | 03/02/2004 |
| 6700831 | Integrated memory having a plurality of memory cell arrays and method for operating the integrated memory An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In order to trigger an access cycle for a memory cell access, a write command or a read command ... | 03/02/2004 |
| 6700828 | Semiconductor memory device The technique of the present invention sets a time period of a level H between a rise and a fall of an ATD signal (that is, a pulse width of the ATD signal) to be not shorter than a preset allowable address skew range and not longer than a time period bet... | 03/02/2004 |
| 6693837 | System and method for quick self-refresh exit with transitional refresh A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is re... | 02/17/2004 |
| 6687325 | Counter with non-uniform digit base A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command.... | 02/03/2004 |
| 6683809 | Nonvolatile memory, IC card and data processing system The invention facilitates to meet both of the mode of use that finds precedence in frequent rewrite to the nonvolatile memory and data retention during the power supply being cut off, and the mode of use that finds precedence in the data retention charact... | 01/27/2004 |
| 6671221 | Semiconductor chip with trimmable oscillator A semiconductor chip, particularly a semiconductor memory, has a trimmable oscillator for controlling internal functions. A circuit is provided for trimming the frequency of the oscillator and is implemented on the semiconductor chip. This guarantees a pa... | 12/30/2003 |
| 6671211 | Data strobe gating for source synchronous communications interface A circuit arrangement and method are used in connection with a data latch that is coupled to a data source over a source synchronous communications interface to disable the data latch from latching data whenever the data source is not driving the source s... | 12/30/2003 |
| 6667929 | Power governor for dynamic RAM Apparatus for limiting the power consumption of a random access memory (RAM), having in combination a counter for counting the number of memory commands in a sample interval, and power governor control logic responsive to the number of memory commands, fo... | 12/23/2003 |
| 6665210 | Data storage and retrieval The invention relates to a method of storing items of data in a memory device. The memory device has an array of a storage locations, each identified by an address corresponding to a unique multi-bit index value. The data items consist of a multi-bit iden... | 12/16/2003 |
| 6662291 | Synchronous DRAM System with control data A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and outpu... | 12/09/2003 |
| 6657920 | Circuit for generating internal address in semiconductor memory device A circuit for generating an internal address in a semiconductor memory device which can reduce power consumption in a self-refresh operation, by generating an internal refresh address to refresh a partial array selected according to an external command in... | 12/02/2003 |
| 6654314 | Semiconductor memory device A method of accessing a semiconductor device that operates in synchronism with a clock signal, including fetching information indicating a memory cell location in a memory cell array in synchronism with the clock signal, determining first data of a plural... | 11/25/2003 |
| 6654292 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 11/25/2003 |
| 6650571 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 11/18/2003 |
| 6650587 | Partial array self-refresh A memory device includes an address selection circuit to store addresses of selected rows of memory cells. During a refresh mode, only the memory cells of the selected rows are refreshed. The addresses of the selected rows can be stored by a user or autom... | 11/18/2003 |
| 6646943 | Virtual static random access memory device and driving method therefor The present invention discloses a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor. When data of the memory cell selected by a received address in a read operat... | 11/11/2003 |
| 6646927 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 11/11/2003 |
| 6646926 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 11/11/2003 |
| 6639854 | Redundancy circuit of semiconductor memory device A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the norma... | 10/28/2003 |
| 6639869 | Clock-synchronous semiconductor memory device A semiconductor device comprises a memory cell array, a counting circuit, a control circuit, a specification circuit, a selection circuit and a data I/O circuit. The selection circuit effects switching between a normal mode and a synchronous mode in a mod... | 10/28/2003 |
| 6636443 | Semiconductor memory device having row buffers A semiconductor memory device has, among other things, a row buffer. The semiconductor memory device includes a memory cell array for storing data, the row buffer for storing data of a row of the memory cell array, and a state machine for controlling the ... | 10/21/2003 |
| 6628560 | Dynamic semiconductor memory device with adjustable refresh frequency A self-refresh timer includes an N-bit counter counting a self-refresh signal, a comparator comparing an output from the counter with a preset value of N-bit width held by a preset value holding circuit, an adder for incrementing, by one, a preset value d... | 09/30/2003 |
| 6625078 | Look-ahead refresh for an integrated circuit memory A circuit and method for an integrated circuit memory incorporates a look-ahead function where refresh commands are presented to the device at least one cycle before actual internal refresh operations occur. Active cycles are executed on the same clock as... | 09/23/2003 |
| 6618293 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 09/09/2003 |
| 6614695 | Non-volatile memory with block erase A method and apparatus for erase operations of a flash memory block. In one embodiment, a method comprises erasing a predetermined percent of rows in a memory block, analyzing a number of erase pulses used to erase the predetermined percent and calculatin... | 09/02/2003 |
| 6606687 | Optimized hardware cleaning function for VIVT data cache A VIVT (virtual index, virtual tag) cache (18) uses an interruptible hardware clean function to clean dirty entries in the cache during a context switch. A MAX counter (82) and a MIN register (84) define a range of cache locations which are dirty. During ... | 08/12/2003 |
| 6600686 | Apparatus for recognizing chip identification and semiconductor device comprising the apparatus A semiconductor device having an apparatus is provided for recognizing chip identification capable of minimizing the number of pads. The apparatus for recognizing chip identification comprises a counter circuit for counting a clock signal in response to a... | 07/29/2003 |
| 6601158 | Count/address generation circuitry According to one embodiment of the invention, an apparatus that includes a first and second counter both including a count computation circuit and an upper bound circuit. The output of the upper bound circuit of the first counter is coupled to the count c... | 07/29/2003 |
| 6597622 | Apparatus and method for operation of multi-bank semiconductor memory device with an up/down counter A multi-bank semiconductor memory device includes a multi-bank memory; a voltage generator having one standby driving circuit and a plurality of active driving circuits and supplying a power source voltage required for a semiconductor device; and, an up/d... | 07/22/2003 |
| 6597605 | Systems with non-volatile memory bit sequence program control Systems including a bit sequence program controller to program in sequence non-volatile memory cells in an array of programmable non-volatile memory cells. The bit sequence program controller determines the bits that require programming by comparing the b... | 07/22/2003 |
| 6594186 | Semiconductor memory and burn-in method for the same A semiconductor memory having a plurality of memory cells includes a first terminal that becomes a power supply terminal for the semiconductor memory, a second terminal that becomes a ground terminal for the semiconductor memory, a third terminal for inpu... | 07/15/2003 |
| 6580659 | Burst read addressing in a non-volatile memory device A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory... | 06/17/2003 |
| 6577547 | Semiconductor memory device The invention provides a semiconductor memory device capable of performing a memory function test without using an expensive tester. When a test enable signal is inputted, a controller 21 makes first selectors 23a and 23b and a second selector 24 select respec... | 06/10/2003 |
| 6577555 | Apparatus for externally timing high voltage cycles of non-volatile memory system An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the ... | 06/10/2003 |
| 6574707 | Memory interface protocol using two addressing modes and method of operation A memory interface (15) and method of use implements a cache (14) bursting addressing technique which begins a read of main memory (16) in a wrap around mode before automatically switching into a linear addressing mode. The use of two modes which automati... | 06/03/2003 |
| 6573748 | Programmable logic device with output register for specifying memory space during reconfiguration Described are programmable logic systems and methods in which programmable logic devices receive configuration data. In some embodiments, one or more input/output blocks of a programmable logic device are adapted to store a value identifying a remote memo... | 06/03/2003 |
| 6570790 | Highly compact EPROM and flash EEPROM devices Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangemen... | 05/27/2003 |
| 6567340 | Memory storage cell based array of counters A multi-counter based system having a counter array. Each counter of the array having a memory cell. The system also includes an address decoder coupled to the counter array to select at least one of the memory cells within the counter array and read/writ... | 05/20/2003 |
