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| Number | Title | Issue Date |
| 6822892 | Resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 11/23/2004 |
| 6819618 | Semiconductor memory device capable of executing refresh operation according to refresh space A semiconductor memory device includes a memory having a predetermined number of divided memory spaces, a register that stores data indicating whether a refresh operation is required or not with respect to each memory space, a row address counter that, with referenc... | 11/16/2004 |
| 6819617 | System and method for performing partial array self-refresh operation in a semiconductor memory device Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or {fraction (1/16)}) of one or more selected memory banks comprising a cell array in... | 11/16/2004 |
| 6813696 | Semiconductor memory device and method of controlling the same The present invention relates to a SDRAM and its control method which write or read data in synchronization with the external clock and its object is to provide a semiconductor memory device and its method which can be easily tested and evaluated by the conventional... | 11/02/2004 |
| 6813208 | System and method for sensing data stored in a resistive memory element using one bit of a digital count A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. ... | 11/02/2004 |
| 6807121 | Semiconductor memory device for realizing external 8K Ref/internal 4K Ref standard without lengthening the refresh cycle A semiconductor memory device is disclosed that realizes the external-8K Ref/internal-4K Ref standard without lengthening the refresh cycle. Successive selection and simultaneous activation of two normal word lines that do not belong to the same mat is first carried... | 10/19/2004 |
| 6804144 | Magnetic random access memory In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, ... | 10/12/2004 |
| 6798695 | Arrangement for storing a count In an arrangement for storing a count, which comprises a non-volatile memory (1) which has at least 3 memory segments (2, 3, 4), a controller (5) is provided which stores a new count in one of the memory segments (2, 3, 4), the controller... | 09/28/2004 |
| 6788617 | Device for generating memory address and mobile station using the address for writing/reading data A device for generating memory addresses is provided that is suitable for generating memory addresses transposed in row/column directions with reference to a data successively stored therein along with a mobile station by using the same, and a method for writing/rea... | 09/07/2004 |
| 6781861 | Method and apparatus for determining digital delay line entry point A method and apparatus to characterize a synchronous device after it is packaged. For synchronous devices, such as SDRAMs implementing a Delay Locked Loop (DLL) to synchronize one signal, such as an external clock signal with a second signal, such as a data signal, ... | 08/24/2004 |
| 6778458 | Dram core refresh with reduced spike current A method for reducing the communication overhead over the interface bus to the memory devices for refresh operations. This is done by refreshing multiple banks in response to a single command. Multibank refresh is made possible by varying the current profile for the... | 08/17/2004 |
| 6771559 | Non-volatile semiconductor integrated circuit A non-volatile semiconductor integrated circuit is provided including a counter circuit that generates column addresses in synchronism with an external clock, and conducts a page programming sequence in word line units, wherein, when inputting program data, the prog... | 08/03/2004 |
| 6765838 | Refresh control circuitry for refreshing storage data A refresh array activating signal is activated in accordance with a refresh request and specific address bit(s) of a refresh address. Specific lower bit(s) of a refresh address counter is (are) utilized as the specific address bit(s) of the refresh address, and the ... | 07/20/2004 |
| 6762974 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read la... | 07/13/2004 |
| 6762963 | Semiconductor memory having dynamic memory cells and a redundancy relief circuit A semiconductor memory capable of reducing refresh cycle time, which includes normal memory cells provided at predetermined intersections of plural normal word lines and plural bit lines, and redundant memory cells of redundant word lines and the plural bit lines, a... | 07/13/2004 |
| 6762962 | Memory system capable of overcoming propagation delay differences during data write DRAM device enters waiting state of write flag on receiving write command from memory controller via external C/A bus, regulator, and internal C/A bus. On receiving the write flag from the memory controller via write flag signal line, the DRAM device uses the write ... | 07/13/2004 |
| 6760274 | Burst read addressing in a non-volatile memory device A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arra... | 07/06/2004 |
| 6757207 | Refresh miss detect circuit for self-refreshing DRAM A counter is incremented whenever an internal refresh is requested and a prior internal refresh request has not yet been completed. A refresh-request storage element such as a latch circuit, provides an output signal that is set upon receipt of an internal refresh r... | 06/29/2004 |
| 6754135 | Reduced latency wide-I/O burst architecture A method for bursting data in a wide I/O memory device with improved access time and reduced data-bus complexity. The memory read operation accesses n bits of data which are output in eight n/8-bit I/O words in any particular order in accordance with the burst base ... | 06/22/2004 |
| 6754126 | Semiconductor memory A plurality of first memory blocks and a second memory block for reproducing data of the first memory blocks are formed. When a read command and a refresh command conflict with each other, a read control circuit accesses the first memory block according to the refre... | 06/22/2004 |
| 6751158 | Bit counter, and program circuit in semiconductor device and method of programming using the same The present invention relates to a bit counter, and a program circuit of a semiconductor device and a program method using the same. Upon a program operation of a word unit, only program data to be programmed among the program data are counted within a pumping perio... | 06/15/2004 |
| 6738309 | Semiconductor memory and method for operating the semiconductor memory A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data o... | 05/18/2004 |
| 6731559 | Synchronous semiconductor memory device A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operati... | 05/04/2004 |
| 6731537 | Non-volatile memory device and data storing method In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a ... | 05/04/2004 |
| 6731567 | DDR memory and storage method The invention relates to a DDR memory and to a storage method for storing data in a DDR memory having a plurality of memory cells which each have a prescribed word length, in which a serial data input is used to read in serial data on a rising or falling edge of the... | 05/04/2004 |
| 6728156 | Memory array system A memory array system is provided comprising a plurality of rows of memory cells, each row having an address, wherein each memory cell stores volatile data requiring periodic refreshing. A refresh controller controls the periodic refreshing of data in each row of me... | 04/27/2004 |
| 6728163 | Controlling a delay lock loop circuit A method and apparatus is provided for performing a filter control of a delay lock loop circuit. A coarse delay and/or a fine delay are implemented upon a reference signal based upon a phase shift between the reference signal and a feedback signal. A synchronized ou... | 04/27/2004 |
| 6724675 | Semiconductor memory device and electronic apparatus A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation. ... | 04/20/2004 |
| 6721224 | Memory refresh methods and circuits A memory performs a hidden refresh only at the end of a read operation or when the memory is disabled but is supposed to retain data in the disabled state. When the memory is in the enabled state, the refresh is not performed at the end of any operation other than r... | 04/13/2004 |
| 6721223 | Semiconductor memory device Data specifying details of refresh to be executed in the self-refresh mode is stored in a register circuit in a mode register. A refresh period and refresh region are determined according to data stored in register circuit and a refresh control circuit generates a c... | 04/13/2004 |
| 6714475 | Fast accessing of a memory device using decoded address during setup time Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address to generate a decoded address. The memory device also inclu... | 03/30/2004 |
| 6714453 | Flash memory including means of checking memory cell threshold voltages A FLASH memory erasable by page includes a flash memory array containing a plurality of floating gate transistors arranged in pages, and a checking circuit for checking the threshold voltages of the floating gate transistors. Programmed transistors that have a thres... | 03/30/2004 |
| 6713778 | Register setting method and semiconductor device A register setting method which facilitates writing of change information into a register for storing operation condition information that defines the operation of a device. The method includes the steps of storing first operation condition information in a first re... | 03/30/2004 |
| 6711093 | Reducing digit equilibrate current during self-refresh mode Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a... | 03/23/2004 |
| 6711084 | Semiconductor device capable of reliable power-on reset The output of a ring oscillator that receives an internal power supply potential as an operating power supply potential to conduct an oscillation operation is counted by a counter that receives an external power supply potential as an operating power supply potentia... | 03/23/2004 |
| 6711082 | Method and implementation of an on-chip self refresh feature Methods, apparatus, and systems for trimming a periodic self-refresh timing signal of a dynamic random access memory (DRAM) device are described. The self-refresh timing signal may be generated by an internal self-refresh circuit including a programmable counter dri... | 03/23/2004 |
| 6711056 | Memory with row redundancy A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together ... | 03/23/2004 |
| 6707757 | Apparatus for externally timing high voltage cycles of non-volatile memory system An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the pulse durat... | 03/16/2004 |
| 6707753 | Low power domino tree decoder An integrated circuit having CMOS domino logic arranged in multistages or a tree structure. The multistage cells and addressing structure may have applications in a decoder and reduce the number of cells being precharged and reduce the operating power. ... | 03/16/2004 |
| 6707743 | Method and apparatus for completely hiding refresh operations in a DRAM device using multiple clock division A method and apparatus for handling the refresh of a DRAM array or other memory array requiring periodic refresh operations so that the refresh does not require explicit control signaling nor handshake communication between the memory array and an external accessing... | 03/16/2004 |
