Did You Know...
...that Charles Goodyear performed some of his experiments on rubber while in debtor's prison? He was there so often he referred to it as his "hotel". Chronically in debt because of poor business sense and ill health, Goodyear depended on the generosity of friends and family. Even after he unlocked the secret to vulcanizing rubber, he was unable to improve his financial situation. When he died, his estate was $200,000 in debt.
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| Number | Title | Issue Date |
| 6948007 | Method and apparatus for configuring integrated circuit devices A method for configuring a plurality of controlling devices includes storing first configuration data for a first one of the controlling devices in a data device. The first configuration data is transmitted from the data device to the first controlling device. Secon... | 09/20/2005 |
| 6947346 | Reducing digit equilibrate current during self-refresh mode Digit equilibrate current is reduced during self-refresh mode by reducing the time that the sub-arrays in a volatile memory are precharged with the bleeder device enabled. A selected sub-array is precharged with the bleeder device enabled one cycle prior to having a... | 09/20/2005 |
| 6944063 | Non-volatile semiconductor memory with large erase blocks storing cycle counts In a flash EEPROM system that is divided into separately erasable blocks of memory cells with multiple pages of user data being stored in each block, a count of the number of erase cycles that each block has endured is stored in one location within the block, such a... | 09/13/2005 |
| 6944256 | Optimizing use of statistics counters Optimizing statistics counter use is disclosed. A total number of counter bits to be used to track two or more statistics is determined. The total number of counter bits is allocated among the two or more statistics to provide for each statistic a counter comprising... | 09/13/2005 |
| 6940756 | Non-volatile memory device with improved sequential programming speed A non-volatile memory device suitable to be programmed in a sequential mode. The device includes a plurality of blocks of memory cells each one for storing a word, each block being identified by an address. An input circuit for loading an input address at the beginn... | 09/06/2005 |
| 6941393 | Pushback FIFO The present invention provides a pushback FIFO architecture that enables a value that has been unloaded from the FIFO to be pushed back into the FIFO at the beginning of the data stream if a determination as made that the data value should not have been unloaded fro... | 09/06/2005 |
| 6937504 | Selecting a magnetic memory cell write current The invention includes an apparatus and method for selecting a desirable magnitude of a magnetic memory cell write current. The method includes determining a minimal magnitude of write current for writing to the magnetic memory cell, determining a maximal magnitude ... | 08/30/2005 |
| 6930931 | Program counter circuit A program counter circuit is composed of two kinds of registers, a down counter, an up counter, a selector, and a logic circuit. The two kinds of registers hold a pre-jump PC value and a post-jump PC value of a jump that is prescribed by a program. The down counter ... | 08/16/2005 |
| 6930946 | Refresh control and internal voltage generation in semiconductor memory device The present invention provides a technique of mitigating the long cycle limitation in a semiconductor memory device that requires refresh operation. A semiconductor memory device comprises a refresh controller that executes refresh operation. The refresh controller ... | 08/16/2005 |
| 6930955 | Method and apparatus for establishing and maintaining desired read latency in high-speed DRAM A method and apparatus for managing the variable timing of internal clock signals derived from an external clock signal in order to compensate for uncertainty and variations in the amount of read clock back timing relative to data flow to achieve a specified read la... | 08/16/2005 |
| 6931086 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 08/16/2005 |
| 6931508 | Device and method for information processing In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to sevent... | 08/16/2005 |
| 6930944 | System and method for power saving memory refresh for dynamic random access memory devices after an extended interval A delay device is added to the addressing and refreshing circuitry of a DRAM array including DRAM devices less volatile than conventional DRAM devices and, thus, need not be refreshed as often. The delay device is connected to intercept refresh signals generated by ... | 08/16/2005 |
| 6928025 | Synchronous integrated memory An output circuit (OUT) can be activated via an activation input (AKT), in the activated state starts an output process for data (D) to be read out, in synchronism with the first internal clock (CLKI1), and outputs the data (D) with a specific phase shift (Δ... | 08/09/2005 |
| 6925522 | Device and method capable of changing codes of micro-controller A device and method capable of changing codes of a micro-controller comprises a micro-controller, an address latch, a flash memory, a static random access memory (SRAM), and a logic circuit. The flash memory has a renovation program and a general program recorded th... | 08/02/2005 |
| 6922456 | Counter system and method A system and method for performing counting operations for a plurality of components is disclosed. A memory stores a plurality of counts from different components. The memory is coupled to a counter and the plurality of counts are accessible to the adder for adding ... | 07/26/2005 |
| 6920539 | Method and system to retrieve information Briefly, in accordance with an embodiment of the invention, a method and system to retrieve information from a memory is provided. The method may include transferring information from the memory in response to at least two synchronous burst read requests using pipel... | 07/19/2005 |
| 6914853 | Mechanism for efficient wearout counters in destructive readout memory A memory device having a wear out counter. The memory device includes at least one block of memory, that block having a metadata section associated with it. A number of bits in the metadata section are used to store the current state of a wear out counter. As the bl... | 07/05/2005 |
| 6914830 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/05/2005 |
| 6912680 | Memory system with dynamic timing correction A memory system includes a memory controller and a bank of memory devices. The memory controller controls the memory devices through packets of control data and a master clock signal. Each of the memory devices includes an adjustable output timing vernier that can b... | 06/28/2005 |
| 6912154 | Magnetic random access memory In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, ... | 06/28/2005 |
| 6909657 | Pseudostatic memory circuit A psuedostatic memory circuit is selected by a memory selection signal. A control circuit, in a first operating mode, carries out a refresh of the memory area at a refresh address after reception of the refresh request signal by generation of a refresh signal if the... | 06/21/2005 |
| 6910096 | SDRAM with command decoder coupled to address registers A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20... | 06/21/2005 |
| 6906948 | Magnetic random access memory In the first read operation, a read current is supplied to TMR elements connected in parallel in one column or one block to detect initial data. Trial data is then written in a selected memory cell. At the same time of or in parallel with writing of the trial data, ... | 06/14/2005 |
| 6895465 | SDRAM with command decoder, address registers, multiplexer, and sequencer A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20... | 05/17/2005 |
| 6895070 | Counter circuit The counter circuit comprises the initial value single port RAM having N initial value registers allocated for memorizing N initial values, the counter register single port RAM having N counter registers allocated for memorizing N counting values, and the control ci... | 05/17/2005 |
| 6879537 | Semiconductor storage device having a plurality of operation modes An operation control circuit is provided for shortening a transition time from a deep stand-by mode to a stand-by mode in a pseudo-SRAM having the deep stand-by mode and the stand-by mode. The transition from the deep stand-by mode to the stand-by mode starts first ... | 04/12/2005 |
| 6865132 | System and method for quick self-refresh exit with transitional refresh A system and method are disclosed to add logic to the self-refresh control logic presently employed in DRAM devices to ensure that, upon transitions between self-refresh mode and operational mode, at least one row of memory cells due to be refreshed is refreshed dur... | 03/08/2005 |
| 6862702 | Address counter for addressing synchronous high-frequency digital circuits, in particular memory devices The novel address counter can be used in combination with an existing test unit—serving for testing digital circuits—for addressing synchronous high-frequency digital circuits, in particular fast memory devices. Address offset values are provided in programmable... | 03/01/2005 |
| 6859407 | Memory with auto refresh to designated banks A memory comprising 2n dynamic random access memory (DRAM) banks, wherein n is an integer greater than or equal to 2, 2n refresh row address counter circuits configured to generate 2n sets of refresh row address signals in response t... | 02/22/2005 |
| 6851013 | Fast program mode A method of programming a memory. The method of one embodiment calls for sending a command to a memory device. The command requests the memory device to enter a program mode. A confirmation of the command is sent. A first address is sent to the memory device. A firs... | 02/01/2005 |
| 6847565 | Memory with row redundancy A memory device is provided. The memory device has a memory array and control circuitry to control operations to the memory array. A redundant register having a bit is also included. The bit is at a first level when two rows of the memory array are shorted together ... | 01/25/2005 |
| 6847561 | Semiconductor memory device A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an addr... | 01/25/2005 |
| 6845060 | Program counting circuit and program word line voltage generating circuit in flash memory device using the same The present invention relates to a program counting circuit and a program word line voltage generating circuit in a flash memory device. The program counting circuit includes a data transmit unit having a plurality of fuses for receiving and transferring data, a cou... | 01/18/2005 |
| 6842840 | Controller which determines presence of memory in a node of a data network A system for determining whether a memory is connected to a controller in a node of a data network. In order to utilize non-volatile memory elsewhere in the system, it is possible to eliminate the EEPROM which is normally connected to the controller. In order to ind... | 01/11/2005 |
| 6839285 | Page by page programmable flash memory An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a suffi... | 01/04/2005 |
| 6829191 | Magnetic memory equipped with a read control circuit and an output control circuit A magnetic memory is disclosed. In one embodiment, the magnetic memory includes first and second memory cells and a read controller coupled to the first and second memory cells. An output controller coupled to the read controller and to the first and second memory c... | 12/07/2004 |
| 6829181 | Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory Testing circuits each including a comparator for comparing data read from semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences, and a counter for counting the number of non-coincidences detected are provide... | 12/07/2004 |
| 6829178 | Nonvolatile memory device A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the pres... | 12/07/2004 |
| 6826104 | Synchronous semiconductor memory In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command ... | 11/30/2004 |
