Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7054204 | Semiconductor device and method for controlling the same Disclosed herein are a semiconductor method and device which are capable of reducing data write errors by rewriting last write data during a write recovery time (tWR). The semiconductor device comprises a memory cell array consisting of a plurality of repetitive cel... | 05/30/2006 |
| 7054218 | Serial memory address decoding scheme A decode circuit for a memory that uses “sequential addressing” includes a series of decoders form a shift register that may be used to provide either wordlines or column select lines for accessing the memory. A pulse generator supplies an appropriate number of ... | 05/30/2006 |
| 7049861 | Reduced current input buffer circuit There is provided an input buffer circuit that, in one embodiment, includes an input buffer adapted to draw an operating current, a first buffer enabling circuitry operatively coupled to the input buffer and adapted to provide a first portion of the operating curren... | 05/23/2006 |
| 7042792 | Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access ... | 05/09/2006 |
| 7042786 | Memory with adjustable access time A memory comprising a memory array, an address buffer configured to receive an external address, a refresh address counter configured to generate a refresh address, a first circuit configured to detect a distance between the external address and refresh address, and... | 05/09/2006 |
| 7038952 | Block RAM with embedded FIFO buffer A programmable logic device includes a block random access memory (“BRAM”) with an embedded first in, first out (“FIFO”) controller. Embedding the FIFO logic in silicon, rather than configuring it in the fabric of the programmable logic device, provides a re... | 05/02/2006 |
| 7027344 | High-speed semiconductor memory having internal refresh control The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores the refresh count address, and the addresses stored in the counter and... | 04/11/2006 |
| 7027336 | Semiconductor memory device for controlling output timing of data depending on frequency variation A semiconductor memory device is capable of controlling the data output timing depending on the operating frequency so as to output data with optimized for the operating frequency. Further, in the high frequency operation, the memory device can output data reliably ... | 04/11/2006 |
| 7027343 | Method and apparatus for controlling refresh operations in a dynamic memory device A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for... | 04/11/2006 |
| 7020038 | Efficient refresh operation for semiconductor memory devices A method and system are disclosed for refreshing a memory module. After identifying a beginning of a memory module for a refreshing operation, at least one address within the memory module being accessed is identified. When the refreshing operation approaches the id... | 03/28/2006 |
| 7020739 | Memory controller, flash memory system having memory controller and method for controlling flash memory device An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of g... | 03/28/2006 |
| 7016451 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 03/21/2006 |
| 7009894 | Dynamically activated memory controller data termination A method is described that involves, for a first read of information from a memory, activating termination loads on a memory controller's side of a data bus between a memory controller and a memory. The method also involves, for a write of information into the memor... | 03/07/2006 |
| 7009901 | System and method for sensing data stored in a resistive memory element using one bit of a digital count A method and system sense the logic state of an unknown initial data bit stored in a selected resistive memory cell. According to one method, a first count representing the logic state of the unknown initial data bit stored in the selected memory cell is generated. ... | 03/07/2006 |
| 7010662 | Dynamic data structures for tracking file system free space in a flash memory device One or more secondary data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each secondary data structure has a predetermined capacity of mappings. A master data structure is also maintained containi... | 03/07/2006 |
| 7007021 | Data structure and method for pipeline heap-sorting An improved data structure is provided by modifying a public-domain data structure known as a “heap”. When these improvements are applied, the resultant data structure is known as a “pile.” This invention further describes a pipelined hardware implementation... | 02/28/2006 |
| 7003619 | Memory device and method for storing and reading a file system structure in a write-once memory array The preferred embodiments described herein provide a memory device and method for storing and reading a file system structure in a write-once memory array. In one preferred embodiment, a plurality of bits representing a file system structure is inverted and stored i... | 02/21/2006 |
| 7003643 | Burst counter controller and method in a memory device operable in a 2-bit prefetch mode A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst co... | 02/21/2006 |
| 7000169 | Turbo decoding Provided are methods and apparatuses for decoding input data by using a single decoder for decoding a first set of symbols and then, after those decoded symbols have been interleaved, using the same decoder for decoding the decoded and interleaved first set of symbo... | 02/14/2006 |
| 6999376 | Burst read addressing in a non-volatile memory device A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arra... | 02/14/2006 |
| 6996660 | Memory device and method for storing and reading data in a write-once memory array The preferred embodiments described herein provide a memory device and method for storing and reading data in a write-once memory array. In one preferred embodiment, a plurality of bits representing data is inverted and stored in a write-once memory array. When the ... | 02/07/2006 |
| 6992948 | Memory device having address generating circuit using phase adjustment by sampling divided clock to generate address signal of several bits having one bit changed in sequential order A semiconductor integrated circuit device is provided in which current consumption is reduced at the time a data access by consecutive addresses is performed to a ROM circuit or a RAM circuit. The semiconductor integrated circuit device incorporates a ROM circuit | 01/31/2006 |
| 6985400 | On-die detection of the system operation frequency in a DRAM to adjust DRAM operations The present invention relates to a memory system including an external clock and a memory chip connected to the external clock. The external clock generates an operating signal at an operating frequency that controls at least one electrical component of the memory s... | 01/10/2006 |
| 6985402 | Programmable address generator A programmable address generator comprising at least one input for receiving a first digital address of a data word in a first memory, to be converted into a second digital address of this same data word in a second memory, or conversely, comprising: at least two hi... | 01/10/2006 |
| 6985372 | Analog content addressable memory (CAM) employing analog nonvolatile storage The invention discloses an analog content addressable memory (CAM) that employs analog storage cells with programmable analog transfer function capability. The analog CAM scans and/or compares its memory array contents to determine if an analog voltage applied at Vi... | 01/10/2006 |
| 6985375 | Adjusting the frequency of an oscillator for use in a resistive sense amp A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed through logic gates to determine whether the sensing output contains a predetermined string of logic ones or ze... | 01/10/2006 |
| 6981126 | Continuous interleave burst access A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read opera... | 12/27/2005 |
| 6975556 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a re... | 12/13/2005 |
| 6976118 | Method and system for programming FPGAs on PC-cards without additional hardware Programming or updating hardware electronic circuits without manually accessing the circuits is dislcosed. The circuit arrangement includes an EEPROM device, a FPGA device which is accessible via a computer bus system and a MUX element connected between said devices... | 12/13/2005 |
| 6973009 | Semiconductor memory device capable of switching between an asynchronous normal mode and a synchronous mode and method thereof A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal af... | 12/06/2005 |
| 6967897 | FeRAM having wide page buffering function A nonvolatile ferroelectric memory device features a wide page buffering function. The nonvolatile ferroelectric memory device comprises a single cell array block, a word line driving unit, a plate line driving unit, a wide page buffer unit and a column selecting un... | 11/22/2005 |
| 6965526 | Sectored flash memory comprising means for controlling and for refreshing memory cells The present invention relates to a method for controlling and for refreshing memory cells in an electrically erasable and programmable memory comprising a memory array organized in sectors, each sector comprising memory cells linked to bit lines and to word lines. T... | 11/15/2005 |
| 6963518 | Semiconductor memory having a pulse generator for generating column pulses A pulse generator generates a plurality of column pulses in response to a read command. An address counter outputs addresses subsequent to an external address supplied in association with the read command in succession as internal addresses. A column decoder success... | 11/08/2005 |
| 6959016 | Method and apparatus for adjusting the timing of signals over fine and coarse ranges A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the... | 10/25/2005 |
| 6954097 | Method and apparatus for generating a sequence of clock signals A clock generator circuit generates a sequence of clock signals equally phased from each other from a master clock signal. The clock generator is formed by inner and outer delay-locked loops. The inner delay-locked loop includes a voltage controlled delay line that ... | 10/11/2005 |
| 6952462 | Method and apparatus for generating a phase dependent control signal A phase detector generates a phase dependent control signal according to the phase relationship between a first and second clock signal. The phase detector includes first and second phase detector circuits receiving the first and second clock signals and generating ... | 10/04/2005 |
| 6952378 | Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations The present invention relates to a method of operating a memory system comprising a memory chip. An operating signal is generated at an operating frequency. The operating frequency is applied to the memory chip to control one or more electrical components of the mem... | 10/04/2005 |
| 6952756 | Method and apparatus for speculative loading of a memory The present invention provides a speculatively loaded memory for use in a data processing system. The present invention may include a memory block including rows each identified by an address. A first register may store a first address of the memory block and a seco... | 10/04/2005 |
| 6949409 | Register setting method and semiconductor device A register setting method which facilitates writing of change information into a register for storing operation condition information that defines the operation of a device. The method includes the steps of storing first operation condition information in a first re... | 09/27/2005 |
| 6948046 | Access controller that efficiently accesses synchronous semiconductor memory device An SDRAM access control section activates a row of an SDRAM when a request is made to access the row in the continuous access mode. The SDRAM access control section outputs a read command or a write command to the SDRAM 300 when a request is made to access th... | 09/20/2005 |
