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| Number | Title | Issue Date |
| 7124256 | Memory device for burst or pipelined operation with mode selection circuitry An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device wi... | 10/17/2006 |
| 7123542 | Memory having internal column counter for compression test mode A memory circuit comprises a memory and an internal column counter for a read sequence in a compression test mode of the memory. The memory comprises an array of memory cells. The internal column counter is configured to provide a first column address for generating... | 10/17/2006 |
| 7120078 | Synchronous semiconductor memory In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command ... | 10/10/2006 |
| 7116578 | Non-volatile memory device and data storing method In a card storage device containing a non-volatile memory and a buffer memory, the buffer memory includes a plurality of banks. Data is transferred sequentially from a host CPU to the banks of the buffer memory, data is transferred to the non-volatile memory from a ... | 10/03/2006 |
| 7116602 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/03/2006 |
| 7113439 | Refresh methods for RAM cells featuring high speed access A method of operating a memory device including an array of cells formed in rows and columns that comprises providing a control signal, activating the control signal, the activated control signal including a first state and a second state, continuously performing ac... | 09/26/2006 |
| 7112984 | System LSI On a clock supply route to a specified block such as a ROM, there are provided a clock delay circuit which includes a plurality of delay elements connected in series and a selector, such that a delay clock signal is selected and output in accordance with a delay con... | 09/26/2006 |
| 7113432 | Compressed event counting technique and application to a flash memory system A non-volatile flash memory system counts the occurrences of an event, such as the number of times that individual blocks have been erased and rewritten, by updating a compressed count only once for the occurrence of a large number of such events. Complementary embo... | 09/26/2006 |
| 7106646 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a re... | 09/12/2006 |
| 7103793 | Memory controller having receiver circuitry capable of alternately generating one or more data streams as data is received at a data pad, in response to counts of strobe edges received at a strobe pad A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data ... | 09/05/2006 |
| 7103742 | Burst/pipelined edo memory device An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device wi... | 09/05/2006 |
| 7103790 | Memory controller driver circuitry having a multiplexing stage to provide data to at least N-1 of N data propagation circuits, and having output merging circuitry to alternately couple the N data propagation circuits to a data pad to generate either a 1x or Mx stream of data A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double dat... | 09/05/2006 |
| 7099208 | Semiconductor memory automatically carrying out refresh operation An arbiter judges which of an internal access request and an external access request takes higher priority, when the internal access request conflicts with the external access request. A redundancy judgement circuit judges which of a normal memory cell and a redunda... | 08/29/2006 |
| 7099234 | Low power sleep mode operation technique for dynamic random access memory (DRAM) devices and integrated circuit devices incorporating embedded DRAM A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary wi... | 08/29/2006 |
| 7099231 | Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system A multi-queue memory system includes first and second memory blocks. The first memory block includes a first array of memory cells, a first sense amplifier circuit and a second sense amplifier circuit. The second memory block includes a second array of memory cells,... | 08/29/2006 |
| 7099221 | Memory controller method and system compensating for memory cell data losses A computer system includes a memory controller coupled to a memory module containing several DRAMs. The memory module also includes a non-volatile memory storing row addresses identifying rows containing DRAM memory cells that are likely to lose data during normal r... | 08/29/2006 |
| 7100090 | Semiconductor memory device having a test circuit A semiconductor memory device includes memory cells, redundant cells, a redundancy repair control circuit and a test mode control circuit. Each of the memory cells is assigned a unique address to be accessed by a corresponding address. The redundant cells are replac... | 08/29/2006 |
| 7095670 | Semiconductor memory having variable memory size and method for refreshing the same A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generate... | 08/22/2006 |
| 7093084 | Memory implementations of shift registers A random access memory array is used as a shift register. Data is written into different locations in a first column of the memory and then gradually transferred successively to any other number of columns in the memory. Such column-to-column data transfer is the re... | 08/15/2006 |
| 7093062 | Flash memory data bus for synchronous burst read page Memory device is described that utilizes a reduced number of sense amplifiers to sense the data bits of a selected column page. The sense amplifiers are multiplexed and the read data values latched, allowing the sense amplifiers to sense the next set of data lines f... | 08/15/2006 |
| 7088632 | Automatic hidden refresh in a dram and method therefor A memory (10) has a plurality of memory cells, a serial address port (47) for receiving a low voltage high frequency differential address signal, and a serial input/output data port (52, 54) for receiving a high frequency low voltage differentia... | 08/08/2006 |
| 7088625 | Distributed write data drivers for burst access memories An address strobe latches a first address. A burst cycle increments the address internally with additional address strobes. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating ... | 08/08/2006 |
| 7085975 | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same Expect data signals are generated for a series of applied data signals having a known sequence to determine if groups of the data signals were properly captured. A first group of the applied data signals is captured, and a group of expect data signals are generated ... | 08/01/2006 |
| 7085192 | Semiconductor integrated circuit device In a semiconductor integrated circuit device, a write command decoder decodes a write command and outputs decode pulses. A command counter circuit counts the decode pulses as the number of commands. A latch circuit latches the write aDDRess in response to a count ou... | 08/01/2006 |
| 7085193 | Clock-synchronous semiconductor memory device A semiconductor device comprises a memory cell array, a control section and a latency setting circuit. The control section configured to receive a clock signal and a control signal, and configured to output a plurality of data in synchronism with the clock signal af... | 08/01/2006 |
| 7085341 | Counter with non-uniform digit base A nonvolatile counter. A nonvolatile storage is organized in digits having non-uniform bases. Circuitry is provided to increment a count value represented by the digits in response to an increment command. ... | 08/01/2006 |
| 7085879 | Dynamic data structures for tracking data stored in a flash memory device One or more mapping data structures are maintained containing mappings of logical flash memory addresses to physical flash memory addresses. Each mapping data structure has a predetermined capacity of mappings. A master data structure is also maintained containing a... | 08/01/2006 |
| 7082075 | Memory device and method having banks of different sizes A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored i... | 07/25/2006 |
| 7076600 | Dual purpose interface using refresh cycle A method and system for optimizing use of signal paths on a DRAM interface. Signal paths that have a ‘don't care’ status during DRAM refresh are assigned to communication with another device. Onset of the refresh procedure triggers diversion of shared signal pat... | 07/11/2006 |
| 7075857 | Distributed write data drivers for burst access memories An integrated circuit memory device is designed to perform high speed data write cycles. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitio... | 07/11/2006 |
| 7073014 | Synchronous non-volatile memory system A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interc... | 07/04/2006 |
| 7068581 | Optical recording apparatus for recording addresses and having a non-consecutive part in which addresses may or may not be set A recordable optical information recording medium having an address t for each sector, comprises: an area A1 starting from an address t1 to which access is made only when a recording apparatus performs recording operation; an area A2 starting fr... | 06/27/2006 |
| 7068558 | Semiconductor memory device having row path control circuit and operating method thereof A semiconductor memory device having a row path control circuit for reducing a peak current. The semiconductor memory device including: a bank controller for activating the bank signal as a first and a second bank driving signals; an inner address counter for genera... | 06/27/2006 |
| 7064987 | Memory address generator with scheduled write and read address generating capability A memory address generator includes a write address generator for generating write addresses to be used in writing of data units of an input data block into a memory device in a non-raster scan arrangement, a read address generator for generating read addresses to b... | 06/20/2006 |
| 7065001 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 06/20/2006 |
| 7061789 | Sensing scheme for programmable resistance memory using voltage coefficient characteristics A method and apparatus for sensing the resistance state of data in a resistance memory cell by using the voltage coefficient of the cell instead of only its resistance. A voltage potential is applied across the resistance memory cell allowing the voltage coefficient... | 06/13/2006 |
| 7061827 | Semiconductor memory device A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is c... | 06/13/2006 |
| 7058839 | Cached-counter arrangement in which off-chip counters are updated from on-chip counters In a first aspect, a counter is maintained in main memory, and a corresponding counter having a smaller number of bits is maintained in cache memory. The counter in cache memory is incremented and when a certain count threshold is reached, the corresponding counter ... | 06/06/2006 |
| 7057945 | Non-volatile memory erase circuitry A non-volatile memory device includes floating gate memory cells, a pulse counter and voltage pump control circuitry. The control circuitry selectively activates pumps in response to a count output of the counter. In one embodiment, the pump output current is increa... | 06/06/2006 |
| 7058732 | Method and apparatus for automatic detection of a serial peripheral interface (SPI) device memory size A method and apparatus for automatically detecting the memory size of a serial peripheral interface (SPI) device. Specifically, the present invention describes an SPI interface circuit including a memory controller chip, an EEPROM, a sensing circuit, and a pulldown ... | 06/06/2006 |
