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| Number | Title | Issue Date |
| 7224638 | Reliability clock domain crossing A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys ... | 05/29/2007 |
| 7221609 | Fine granularity DRAM refresh A method, device, and system are included. In one embodiment, the method included issuing a single row refresh command for a first row in a memory starting at a target address, incrementing a row counter, continuing issuing a single row refresh command for each subs... | 05/22/2007 |
| 7221612 | SDRAM address mapping optimized for two-dimensional access Typically, a bulk of the memory space utilized by an SOC (103) is located in cheaper off-chip memory devices such as Synchronous Dynamic Random Access Memory (SDRAM) memories (104). These memories provide a large capacity for data storage, at a relativ... | 05/22/2007 |
| 7219170 | Burst transfer register arrangement Machine-readable media, methods, and apparatus are described to burst write a command and its arguments to control registers of a device and to burst read status and outputs of the command from control registers of the device. During the burst write, the arguments m... | 05/15/2007 |
| 7215589 | Semiconductor memory device that requires refresh operations A semiconductor memory device includes a refresh counter that outputs an address of a word line to be refreshed, a ROM circuit that stores a relevant address related to a refresh defective address, and a multiple refresh control circuit that simultaneously or contin... | 05/08/2007 |
| 7206246 | Semiconductor memory device, refresh control method thereof, and test method thereof The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh... | 04/17/2007 |
| 7206239 | Semiconductor device and skew adjusting method Function circuits composing one function macro are divided and mounted on plural chips, plural internal clock signals having different phases with one another are generated based on a clock signal to be a reference, a phase of a clock signal supplied to the function... | 04/17/2007 |
| 7203126 | Integrated circuit systems and devices having high precision digital delay lines therein An integrated circuit delay device includes a digital delay line configured to provide a percent-of-clock period delay to a timing signal received at an input thereof, in response to a control signal. This control signal has a value that specifies a length of the de... | 04/10/2007 |
| 7196967 | Semiconductor integrated circuit A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency o... | 03/27/2007 |
| 7193929 | Semiconductor integrated circuit A semiconductor integrated circuit includes a memory circuit, an oscillator circuit which generates an internal clock signal, based on control information held in the memory circuit, and a logic circuit which generates control information that causes the frequency o... | 03/20/2007 |
| 7193927 | Memory device and method having banks of different sizes A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored i... | 03/20/2007 |
| 7190619 | Circuit for indicating termination of scan of bits to be programmed in nonvolatile semiconductor memory device A circuit for indicating termination of scan of bits to be programmed in a nonvolatile semiconductor memory device includes a counting unit, a set bit number provision unit and a comparison unit. The counting unit counts the predetermined number of bits to be progra... | 03/13/2007 |
| 7188211 | Block programmable priority encoder in a CAM A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical... | 03/06/2007 |
| 7184324 | Semiconductor memory device having a single input terminal to select a buffer and method of testing the same A semiconductor memory device has a single input terminal to select a buffer and includes input-output terminals, input-output buffers, a memory core, and a buffer selecting unit. The input-output terminals include address input terminals, data input-output terminal... | 02/27/2007 |
| 7177223 | Memory device and method having banks of different sizes A memory device, such as a synchronous random access memory device, includes four banks of memory cells arranged in rows and columns. Different numbers of columns of memory cells are contained in each of the four banks. The bank in which an item of data are stored i... | 02/13/2007 |
| 7173845 | User RAM flash clear A memory cell includes first and second p-channel transistors and first and second n-channel transistors in a cross-coupled latch configuration. Power control circuitry associated with the memory cell is coupled to selectively perform voltage transitions on the sour... | 02/06/2007 |
| 7173610 | Decoder system capable of performing a plural-stage process A decoding system which is arranged to perform a plural-stage process in determining which of the driver lines to stimulate in response to each electrode address value supplied to the decoder. This enables the network configuration of the impedances to be machine ge... | 02/06/2007 |
| 7170819 | Integrated semiconductor memory device for synchronizing a signal with a clock signal A semiconductor memory includes a control circuit for generating an internal read command signal depending on an externally applied read command signal. A clock generating circuit generates a system clock signal and a time shifted clock signal generated by a DLL cir... | 01/30/2007 |
| 7164613 | Flexible internal address counting method and apparatus A method of controlling an internal address counter which provides a count used in accessing a storage cell array to provide increased flexibility in the performance of a test on the array, comprising, rendering a normal overflow condition of the counter modified, t... | 01/16/2007 |
| 7164617 | Memory control apparatus for synchronous memory unit with switched on/off clock signal In a memory control apparatus for controlling a synchronous memory unit, the apparatus receives a source clock signal, switches ON and OFF the source clock signal in accordance with an access request signal to the synchronous memory unit and an idle state with no ac... | 01/16/2007 |
| 7158407 | Triple pulse method for MRAM toggle bit characterization A method is provided for testing magnetic bits (3, 104, 514) of an array. A train of first (702), second (704), and third (706) pulses is provided to a desired bit, the first and second pulses beginning at a substantially similar low fiel... | 01/02/2007 |
| 7158444 | Semiconductor memory device A semiconductor memory device comprises a memory cell array and a control circuit. The memory cell array has a plurality of memory cells arranged in rows and columns. The memory cells store data and are selected according to address signals. The control circuit is c... | 01/02/2007 |
| 7158426 | Method for testing an integrated semiconductor memory An integrated semiconductor memory can be operated in a normal operating state synchronously with a control clock. In the test operating state, the integrated semiconductor memory is driven synchronously with a clock edge of the control clock with a first control si... | 01/02/2007 |
| 7159092 | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same A method and circuit adaptively adjust respective timing offsets of digital signals relative to a clock output along with the digital signals to enable a latch receiving the digital signals to store the signals responsive to the clock. A phase command for each digit... | 01/02/2007 |
| 7158418 | Non-volatile memory device capable of changing increment of program voltage to mode of operation A non-volatile memory device includes a word line voltage generator circuit for generating a word line voltage to be supplied to a selected row in response to step control signals, and a program controller for generating the step control signals so that an increment... | 01/02/2007 |
| 7151689 | Adjusting the frequency of an oscillator for use in a resistive sense amp A system and methods optimize the operation of sensing circuitry. In one embodiment, the output of a sensing circuit is stored in a register and processed through logic gates to determine whether the sensing output contains a predetermined string of logic ones or ze... | 12/19/2006 |
| 7149824 | Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device. ... | 12/12/2006 |
| 7145829 | Single cycle refresh of multi-port dynamic random access memory (DRAM) A multi-port DRAM having refresh cycles interleaved with normal read and write operations implements a single cycle refresh sequence by deferring the write portion of the sequence until the next refresh cycle. During a single clock cycle, the system writes stored da... | 12/05/2006 |
| 7145814 | RAS time control circuit and method for use in DRAM using external clock There is provided a RAS time control circuit for use in a semiconductor memory device. The RAS time control circuit includes a counter for counting the number of external clocks, a comparator for comparing the counted clock number with a preset comparison reference ... | 12/05/2006 |
| 7142475 | Memory device having a configurable oscillator for refresh operation A dynamic random access memory device includes banks of dynamic memory cells. The device performs a refresh operation in response to receiving a self refresh command, by refreshing rows of the memory cells located in each of the banks. Further, a refresh frequency f... | 11/28/2006 |
| 7143257 | Method and apparatus of a smart decoding scheme for fast synchronous read in a memory system An apparatus and method identify a plurality of words to be read, read these selected words during a clock latency period, and then shift these words out synchronously at an end of the latency period. In another aspect of the present invention, the above method of r... | 11/28/2006 |
| 7142468 | Control method of semiconductor memory device and semiconductor memory device It is intended to provide a control method of a semiconductor memory device and a semiconductor memory device capable of shortening pre-charge operation time that comes after termination of successive data access operation, namely, successive data read/write operati... | 11/28/2006 |
| 7139216 | Semiconductor storage device having a counter cell array to store occurrence of activation of word lines A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality... | 11/21/2006 |
| 7139193 | Non-volatile memory with two adjacent memory cells sharing same word line A nonvolatile semiconductor memory device having a small layout size includes a memory cell array in which a plurality of memory cells are arranged in a row direction and a column direction. The memory cell array includes a plurality of element isolation regions. Ea... | 11/21/2006 |
| 7137024 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 11/14/2006 |
| 7133992 | Burst counter controller and method in a memory device operable in a 2-bit prefetch mode A burst counter generates all but the least significant bit (“LSB”) of a sequence of column addresses in a 2-bit prefetch dynamic random access memory (“DRAM”). The sequence of column addresses is generated by either incrementing or decrementing the burst co... | 11/07/2006 |
| 7133307 | Resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 11/07/2006 |
| 7133312 | Readout circuit for semiconductor memory device based on a number of pulses generated by a voltage-controlled oscillator By a first readout, the current input from a selected cell is converted by a preamplifier and a voltage-controlled oscillator into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is count... | 11/07/2006 |
| 7130241 | Semiconductor memory device having different synchronizing timings depending on the value of CAS latency A semiconductor memory device including a clock buffer, a column selection line decoder, a control signal generation circuit, and a column selection line driver. The clock buffer receives an external clock signal and information about a column address strobe (CAS) l... | 10/31/2006 |
| 7130233 | Sensing circuit for single bit-line semiconductor memory device A sensing circuit for sensing logic data is shown. A memory cell is electrically connected to a bit line. The sensing circuit includes a first pre-charging module electrically connected to the bit line for pre-charging the bit line. A selecting module is electricall... | 10/31/2006 |
