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| Number | Title | Issue Date |
| 7345950 | Synchronous semiconductor memory device A synchronous semiconductor memory device of the present invention has a clock generator for generating a normal and a reverse phase clocks by dividing an external clock, a command decoder for decoding an external command and outputting a command signal; latency set... | 03/18/2008 |
| 7342835 | Memory device with pre-fetch circuit and pre-fetch method A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read da... | 03/11/2008 |
| 7342841 | Method, apparatus, and system for active refresh management A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus r... | 03/11/2008 |
| 7334093 | Block programmable priority encoder in a CAM A priority encoder (PE) for a CAM, comprising a plurality of PE blocks, each receiving a plurality of match results corresponding to data entries in a corresponding data array block and, for determining an address of a highest priority data entry based on a physical... | 02/19/2008 |
| 7330929 | CAM modified to be used for statistic calculation in network switches and routers A content addressable memory (CAM) device includes a plurality of entries each having an associated counter. When a CAM entry matches a search word stored in the comparand register of the CAM device, the matching entry's counter may be incremented. Alternatively, if... | 02/12/2008 |
| 7330951 | Apparatus and method for pipelined memory operations A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and... | 02/12/2008 |
| 7330381 | Method and apparatus for a continuous read command in an extended memory array The present invention relates to a memory on a silicon microchip, comprising a serial input/output and an integrated memory array addressable under N bits. According to the present invention, the memory comprises means for storing a most significant address allocate... | 02/12/2008 |
| 7321520 | Configurable length first-in first-out memory A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for... | 01/22/2008 |
| 7319612 | Performing multiple read operations via a single read command In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from the plurality of read operations in a volatile array of the memory. ... | 01/15/2008 |
| 7319635 | Memory system with registered memory module and control method A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal... | 01/15/2008 |
| 7320081 | Clock-signal generation device, communication device, and semiconductor device A clock-signal generation device which changes an average frequency of a clock signal independently of a reference clock signal. A reference-clock-signal generation circuit generates a reference clock signal. A frequency-division circuit divides the frequency of the... | 01/15/2008 |
| 7310262 | Ferroelectric memory capable of continuously fast transferring data words in a pipeline A storage device including a ferroelectric memory cell array including a plurality of memory cells; sense amplifiers connected to the bit lines and selected by a column address; an internal counter able to generate the column address; and a control part controlling ... | 12/18/2007 |
| 7307899 | Reducing power consumption in integrated circuits A method and apparatus for reducing power consumption in integrated memory devices is provided. Banks of memory cells may be individually put into “sleep” mode via respective “sleep” transistors. ... | 12/11/2007 |
| 7304910 | Semiconductor memory device with sub-amplifiers having a variable current source A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two ki... | 12/04/2007 |
| 7302029 | Counting circuit for controlling an off-chip driver and method of changing an output current value of the off-chip driver using the same Provided is a counting circuit for controlling an off-chip driver and method of changing a DC output current value of the off-chip driver using the same in accordance with variations of processing characteristics with PMOS and NMOS in the state of wafer level. The c... | 11/27/2007 |
| 7301824 | Method and apparatus for communication within an integrated circuit Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network. ... | 11/27/2007 |
| 7298658 | Semiconductor memory device using row redundancy and I/O redundancy scheme based on a preset order and a defect order To reduce the area relating to location of redundant elements for relieving defects of a memory. A memory device has row address and input/output data as two dimensional redundancy parameters for relieving defects of an embedded memory 30. It comprises a buil... | 11/20/2007 |
| 7292477 | Nonvolatile semiconductor memory device which stores multivalue data A voltage generating circuit supplies first gate voltage to the control gate of a memory cell for a first control time period and supplies write voltage to the drain for a first write time period which is shorter than the first control time period when an operation ... | 11/06/2007 |
| 7292471 | Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so ... | 11/06/2007 |
| 7292491 | Method and apparatus for controlling refresh operations in a dynamic memory device A method and apparatus are provided for controlling refresh operations of a dynamic memory device. The temperature of the dynamic memory device is detected. The detected temperature is then used to adjust a refresh rate of the dynamic memory device to compensate for... | 11/06/2007 |
| 7289371 | Semiconductor memory device and electronic equipment A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a wri... | 10/30/2007 |
| 7290078 | Serial memory comprising means for protecting an extended memory array during a write operation The present invention relates to a memory on a silicon microchip, having a serial input/output, an integrated memory array addressable under N bits, and at least one register that is read accessible, after applying a command for reading the register to the memory. T... | 10/30/2007 |
| 7289381 | Programmable boosting and charge neutralization A programmable capacitance circuit including an input node; an output node; and a plurality of capacitance stages. Each of the capacitance stages is coupled to the input node and the output node, and wherein each capacitance stage is configured to be switched into a... | 10/30/2007 |
| 7286401 | Nonvolatile semiconductor memory device Disclosed here is a nonvolatile semiconductor memory device used to prevent data loss that might occur in unselected memory cells due to a disturbance that might occur during programming/erasing in/from those memory cells. In the nonvolatile semiconductor memory dev... | 10/23/2007 |
| 7277345 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/02/2007 |
| 7274602 | Storage device and control method therefor The conductance of a first switch circuit (T1) is periodically controlled in response to an error-amplification circuit (A1) whereby electric power, stored in an inductance circuit (L1) from INPUT VOLTAGE VIN, is released, through a rectifier ci... | 09/25/2007 |
| 7275130 | Method and system for dynamically operating memory in a power-saving error correcting mode A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubb... | 09/25/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7269068 | Flash memory device and method of programming the same Flash memory devices include a memory array having a plurality of NAND strings of EEPROM cells therein. A word line driver is provided to improve programming efficiency. The word line driver is electrically coupled to the memory array by a plurality of word lines. T... | 09/11/2007 |
| 7269084 | Semiconductor memory device The disclosure concerns a semiconductor memory device that includes memory cells that store data by accumulating or discharging an electric charge; memory cell arrays having a plurality of the memory cells disposed in a matrix; a plurality of word lines connected to... | 09/11/2007 |
| 7263009 | Semiconductor memory device with delay section In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value w... | 08/28/2007 |
| 7260013 | Power supply device in semiconductor memory A power supply device in a semiconductor memory includes a power control means and a power generation means. The power control means divides a self-refresh section into an active-precharge mode and an idle mode depending on an operation characteristic of the semicon... | 08/21/2007 |
| 7260011 | Semiconductor storage device and refresh control method therefor A dynamic semiconductor storage device in which the power supply current during the standby time is diminished to decrease the power consumption and to suppress the chip area from increasing. During the normal operation, the information as to a word line associated ... | 08/21/2007 |
| 7257045 | Uni-stage delay speculative address decoder An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n−1 inputs, the n−1 inputs being a subset of n inputs conveyed to each decoder circuit. Each deco... | 08/14/2007 |
| 7254072 | Semiconductor memory device having hierarchically structured data lines and precharging means A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a c... | 08/07/2007 |
| 7251180 | Semiconductor memory device An apparatus a counter, storage units for storing count values interrupted by a row address whose refresh period is subject to change; comparator circuits for comparing the counter outputs and the contents of the storage units to each other as to whether or not the ... | 07/31/2007 |
| 7245556 | Methods for writing non-volatile memories for increased endurance A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on ... | 07/17/2007 |
| 7234070 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding A memory system includes a memory hub controller that sends write data to a plurality of memory modules through a downstream data bus and receives read data from the memory modules through an upstream data bus. The memory hub controller includes a receiver coupled t... | 06/19/2007 |
| 7230495 | Phase-locked loop circuits with reduced lock time PLL circuits are provided in which a voltage-controlled oscillator (VCO) comprising one or more voltage-controlled delay units (VCDs) is initialized with the control voltage of a voltage-controlled delay line (VCDL) having substantially identical VCDs. In general, V... | 06/12/2007 |
| 7228470 | Semiconductor testing circuit, semiconductor storage device, and semiconductor testing method A semiconductor testing circuit being arranged for testing a semiconductor storage device, and having a simple construction and a great number of executable test patterns. Counters designate portions of a write/read address by count values outputted from the counter... | 06/05/2007 |
