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A vest or belt is integrally formed with tubular, pet receiving passageways which extend around the wearer's body and terminate in pocket-like chambers for feeding and retrieval.
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| Number | Title | Issue Date |
| 4633441 | Dual port memory circuit Dual port memory which enables consecutive access operations from an arbitrary address. The memory includes a memory array, a random access peripheral circuit for effecting random access to the array, a counter, a setting circuit for setting the counting ... | 12/30/1986 |
| 4623986 | Memory access controller having cycle number register for storing the number of column address cycles in a multiple column address/single row address memory access cycle This device permits the distribution of the access to a RAM memory RAM (14) among a plurality of users (U1, U2, U3), the access being effected in an asynchronous manner. Certain users (U2, for example) can access the memory at adjoining addresses by means... | 11/18/1986 |
| 4618947 | Dynamic memory with improved address counter for serial modes A semiconductor dynamic read/write memory device has serial data input/output modes, such as the so-called nibble, byte or extended nibble modes. This device employs improved address counter circuitry to access data from a selected row. An initial column ... | 10/21/1986 |
| 4581721 | Memory apparatus with random and sequential addressing A memory apparatus suitable for storing data for a high resolution bit mapped display includes large capacity (e.g. 64-k) semiconductor random access memory circuits in which to reduce the effective access time the circuits are operated and addressed in a... | 04/08/1986 |
| 4551822 | Dynamic semiconductor memory device A dynamic semiconductor memory device having a refresh-address generator, includes an initial resetting circuit for resetting the output signals of a refresh-address counter when the power supply is turned on, thereby eliminating the need for counter chec... | 11/05/1985 |
| 4549283 | Digital time delay circuit with high speed and large delay capacity A delay circuit including an even number of memory devices, for example two, reading from one memory device, while writing to the other. Sequences of bit addresses are generated for writing and reading, with an offset between the sequences. For the case o... | 10/22/1985 |
| 4528648 | Memory management system A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.... | 07/09/1985 |
| 4513400 | Circuit for reading out address data applied to a memory in a one-chip microcomputer A circuit for reading out address data applied to a memory in a one-chip microcomputer which does not have any address terminals but has input/output terminals. The circuit comprises a program counter for specifying reading out addresses of the memory. Tr... | 04/23/1985 |
| 4509142 | Semiconductor memory device with pipeline access A semiconductor memory device contains an on-chip self-incrementing counter which may be loaded from address input terminals, so that the memory cell array may be accessed using either an incoming address or the last address incremented by one. Also, the ... | 04/02/1985 |
| 4506348 | Variable digital delay circuit A variable digital delay circuit is disclosed which utilizes a shift register to periodically sample a signal to be delayed and after a predetermined number of samples are collected as a group of zeros and ones making up a binary word the word is stored i... | 03/19/1985 |
| 4467458 | Read-only sequence controller A small size sequence controller for a read-only memory in which data stored in a read-only memory (4) are read out sequentially to operate an output relay during a time interval in accordance with the stored data, and the relay controls a load. Clock pul... | 08/21/1984 |
| 4458357 | Circuit board identity generator A plurality of identical circuit board identification generators are individually located on an associated plurality of circuit boards in a computer system, each generator providing a unique identification for each associated circuit board. Identification... | 07/03/1984 |
| 4403310 | Fixed data reading system Disclosed is a fixed data reading system which comprises a read only memory for storing program data and fixed data, a random access memory for storing non-program data, a program counter for specifying a location of the read only memory, an incrementer f... | 09/06/1983 |
| 4394753 | Integrated memory module having selectable operating functions An integrated memory module has operating functions which are selectable even after the module has been built-in. A significant expansion of the possibilities of use of the memory module is achieved by the introduction of an inscribable and readable mode ... | 07/19/1983 |
| 4393482 | Shift register A shift register of the type capable of performing shift operations by changing the access of a random access memory, which is capable of performing the operations at a high speed, with respect to the address for reading data and the output of a counter, ... | 07/12/1983 |
| 4387446 | Stack control system A stack control system serves for transferring information issued from an information source to an information receiving unit through a stack unit which includes a plurality of stacks for storing therein the information from the information source, the in... | 06/07/1983 |
| 4369504 | Serial-parallel signal converter A serial-parallel converter for storing sequentially a serially input digital signal in a predetermined number of elements and producing the stored data at one time as a parallelly output digital signal. The serially input digital signal is sequentially w... | 01/18/1983 |
| 4366557 | Circuit arrangement for the recognition of predetermined binary valves of a specific minimum duration A circuit arrangement recognizes predetermined binary values of a specific minimum duration. Data from a plurality of data sources are emitted to a common data line by way of a respective switch. An address generator periodically generates data source add... | 12/28/1982 |
| 4354232 | Cache memory command buffer circuit In a computer system, with a system interface unit (SIU) for controlling data transfers between a lower speed main memory and either a central processor unit (CPU) or a high-speed cache memory unit (CMU), a cache memory command buffer (CMCB) circuit allow... | 10/12/1982 |
| 4295205 | Solid state mass memory system compatible with rotating disc memory equipment A solid state mass memory system, utilizing memory units other than rotating disc memories, compatible with existing external rotating disc memory equipment designed to operate in conjunction with rotating disc memory units only, includes means for simula... | 10/13/1981 |
| 4280199 | Apparatus for scanning an addressable memory Apparatus for scanning an addressable memory includes a clock pulse generator and an address counter for counting the clock pulses so as to produce an address for the addressable memory and thereby designate a corresponding storage location from which sto... | 07/21/1981 |
| 4233673 | Electrically resettable non-volatile memory for a fuse system A non-volatile memory has a plurality of storage bits, each bit comprising an insulated gate field effect transistor having a variable threshold voltage and selectively set to first and second stable threshold voltages in response to the application of po... | 11/11/1980 |
| 4206476 | Control circuit for use with a time-compression/time-expansion system in a pulse signal record/playback device A system for using a video signal recorder/playback device of the type normally adapted to record and/or reproduce video signals on a record medium, for recording and/or reproducing pulse signals on the record medium. The system includes time-compression/... | 06/03/1980 |
| 4198699 | Mass memory access method and apparatus A method and apparatus for transferring digital data between a mass memory and a random access memory. The mass memory has a plurality of memory loops, each having a plurality of memory cells, and a read/write device which either outputs data from the mem... | 04/15/1980 |
| 4187539 | Pipelined data processing system with centralized microprogram control A pipelined data processing system having n processing stages, each of which is under the control of a central microprogram. Each microprogram instruction is decoded to produce n control signals, one for each processing stage. Microprogram start addresses... | 02/05/1980 |
| 4171538 | Elastic store slip circuit apparatus for preventing read and write operations interference A method of and circuitry for the operations of reading from and writing into a memory, each of which operations occurs on a sequential basis and each of which has different clock rates while preventing erroneous information from being read due to interfe... | 10/16/1979 |
| 4159538 | Associative memory system An associative memory system in large-scale-integrated semiconductor technology comprises word-organized and bitwise maskable fully associative memory devices which can be arranged in a memory array with a plurality of rows and columns and a control unit ... | 06/26/1979 |
| 4133041 | Data processing control apparatus with selective data readout A data processing control apparatus comprises a main memory for storing a plurality of record data serially arranged with a record positioning code between the record data, each record data including a plurality of word data serially arranged with a word ... | 01/02/1979 |
| 4128879 | Recirculating memory with plural input-output taps A CCD (charge coupled device) RAM (random access memory) includes a plurality of "rings" of serially connected CCDs in which digital information recirculates. A combinational decoder selects one of the plurality of rings by decoding a first group of binar... | 12/05/1978 |
| 4125879 | Double ended stack computer store The invention provides a computer store having successively addressed storage locations for individual words grouped together to form so-called clotheslines. Data can be written into and read out from either end of a clothesline. A clothesline thus combin... | 11/14/1978 |
| 4046995 | Memory fullness indicator A digital card reader is connected to supply input data to a random access memory corresponding to pre-coded information on cards inserted into the reader. The insertion of a card into the reader causes a binary counter to advance one binary count to addr... | 09/06/1977 |
| 3993982 | Sequence control unit for a television time base corrector A sequence control unit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converte... | 11/23/1976 |
| 3992702 | Code conversion arrangements for addresses to faulty memory locations A code converter comprising a pair of memories which are addressed by respective halves of the input code. The outputs of the memories are concatenated to provide an address for a third memory. The output of the third memory provides the output code. The ... | 11/16/1976 |
