Quotables
"There is no likelihood man can ever tap the power of the atom."
Robert Millikan, Nobel Prize winner in physics
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6219289 | Data writing apparatus, data writing method, and tester A data writing apparatus for writing data to a plurality of electric devices, comprising: a pattern memory which stores a plurality of said data to be written to at least one of said electric devices; an ALPG and an address selector which output said plur... | 04/17/2001 |
| 6215726 | Semiconductor device with internal clock generating circuit capable of generating internal clock signal with suppressed edge-to-edge jitter A data/strobe output buffer performs data output according to an outputting internal dock signal DLLCLK from a DLL (Delayed Locked Loop) circuit and an output enable signal. During a time period for a data reading operation including a time period in whic... | 04/10/2001 |
| 6215837 | Pipe counter signal generator processing double data in semiconductor device Disclosed is a DDR SDRAM device which may be implemented by simply modifying a pipe counter for an SDR SDRAM device. A pipe counter comprising according to the present invention comprises: a controller for producing a counter control signal in response to... | 04/10/2001 |
| 6215729 | Programmable counter circuit for generating a sequential/interleave address sequence A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of a burst counter circuit are multiplexed to send t... | 04/10/2001 |
| 6195731 | Instrumentation device for a machine with non-uniform memory access A machine with non-uniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), each module comprising a unit (6, 26, 46, 66), the unit (6) comprising at least one table (8) for managing local accesses to a memory p... | 02/27/2001 |
| 6195309 | Timing circuit for a burst-mode address counter A burst-mode capable RAM chip includes a timing circuit for clocking a burst counter during a burst transfer. In response to an input indicating the beginning of the burst transfer, the timing circuit generates a first signal that loads the initial addres... | 02/27/2001 |
| 6195728 | Detection of hot points in a non-uniform memory access machine A data processing machine with nonuniform memory access and cache coherency is constituted by a plurality of modules (10, 20, 40, 60), a given module (10) including a unit (6) to assure data coherence with other modules (20, 40, 60), characterized in that... | 02/27/2001 |
| 6195304 | Semiconductor memory device and its refresh address signal generating method adapted to reduce power consumption during refresh operation A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the ... | 02/27/2001 |
| 6192002 | Memory device with command buffer A memory device includes a memory array, an external clock terminal, and control logic. The memory array is arranged in rows and columns. The external clock terminal is adapted to receive an external clock signal. The external clock signal has at least a ... | 02/20/2001 |
| 6188627 | Method and system for improving DRAM subsystem performance using burst refresh control A method and system for improving DRAM performance using burst refresh control reduces the overhead associated with refreshing DRAM in a computer system, making the memory more available to the devices that access it. Limiting the burst cycle to less than... | 02/13/2001 |
| 6188640 | Data output circuits for semiconductor memory devices A data output circuit for a semiconductor memory device, such as a synchronous DRAM (SDRAM) includes an output control circuit that acquires a command in sync with an input internal clock signal and generates an output control signal used to determine the... | 02/13/2001 |
| 6185134 | Flash memory control method, flash memory system using the control method and flash memory device using the control method A method of correcting errors of a flash memory comprises steps of modifying the data of a group of memory units, each having a plurality of flash memory cells adapted to erasing data therefrom and writing data therein, checking for the presence or absenc... | 02/06/2001 |
| 6175535 | Cycle control circuit for extending a cycle period of a dynamic memory device subarray A cycle control circuit for use with a memory device subarray and method of operation thereof. The cycle control circuit includes a previous address buffer for storing a last accessed address of the subarray and an address comparator for comparing a curre... | 01/16/2001 |
| 6166991 | Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate (i) an internal select signal and (ii) a control signal in response to one or more chip select signals. The second circuit may be configured to g... | 12/26/2000 |
| 6147926 | Semiconductor memory device Semiconductor memory device which can support a DDR SDRAM latency mode like 2.5 for easy application to a high data rate memory, including a memory cell array having a plurality of memory cell regions for storing external data and forwarding the data on t... | 11/14/2000 |
| 6147921 | Method and apparatus for optimizing memory performance with opportunistic refreshing A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the... | 11/14/2000 |
| 6130853 | Address decoding scheme for DDR memory Circuits and a method are disclosed for a semiconductor memory which decode from a system supplied input address two outputs which are either adjacent or boundary adjacent to each other. The two decoded outputs derived from the input address select then, ... | 10/10/2000 |
| 6128248 | Semiconductor memory device including a clocking circuit for controlling the read circuit operation A semiconductor memory device is provided which includes a memory cell array, a read circuit which reads data from said memory cell array, and an external terminal which receives an external clock signal. A first input circuit receives the external clock ... | 10/03/2000 |
| 6128692 | Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices A programmable logic array integrated circuit device has a relatively large block of programmable memory cells in addition to the usual programmable logic modules and the usual programmable interconnection conductor network. In order to simplify the circu... | 10/03/2000 |
| 6115280 | Semiconductor memory capable of burst operation A semiconductor memory for operating in burst mode. The memory has a memory cell array divided into a plurality of memory blocks, a plurality of (e.g., 2) output registers each including a plurality of output data retaining blocks corresponding to the mul... | 09/05/2000 |
| 6111815 | Synchronous burst nonvolatile semiconductor memory A synchronous semiconductor burst nonvolatile semiconductor memory includes first and second address counter circuits and a counter selection circuit in order to output an address signal to a first latch circuit for storing therein data from a memory cell... | 08/29/2000 |
| 6111810 | Synchronous semiconductor memory device having burst access mode and multi-bit pre-fetch operation The present invention provides a synchronous memory device having at least a multi-bit pre-fetch address generator circuit, and at least an access path which includes at least a command decoder having an output terminal connected to at least a follower ci... | 08/29/2000 |
| 6108265 | Semiconductor memory A semiconductor memory comprises two banks each including a number of memory cells arranged in the form of a matrix having a plurality of rows and a plurality of columns, each of the banks having a plurality of data input/output lines extending in a colum... | 08/22/2000 |
| 6104669 | Method and apparatus for generating memory addresses for testing memory devices A counter internal to a memory device for generating memory addresses in physical or logical sequence in non-redundant or redundant memory space, counting up or down in increments of the user's choice. The counter may be advantageously used to generate me... | 08/15/2000 |
| 6104664 | Memory address generator circuit and semiconductor memory device A semiconductor storage device (1100) having a burst mode capability for accomplishing a rapid read/write operation is disclosed. Included is a memory address generator circuit (100) having an address counter (102) which latches and increments the n least... | 08/15/2000 |
| 6101136 | Signal delay device for use in semiconductor storage device for improved burst mode operation A semiconductor storage device (100) having a burst mode capability for accomplishing a rapid pipeline operation is disclosed. A signal delay device (104), such as a first-in-first-out buffer (FIFO), is disposed between the data read circuitry of a memory... | 08/08/2000 |
| 6092164 | Microcomputer having division of timing signals to initialize flash memory A microcomputer comprising a CPU for outputting a signal requesting generation of pulses when receiving an erase signal requesting processing to initialize a flash memory unit; a timer for generating the pulses when receiving the signal requesting generat... | 07/18/2000 |
| 6091665 | Synchronous random access memory having column factor counter for both serial and interleave counting A synchronous dynamic random access memory (SDRAM) improves memory access time by incorporating into the column address path a bidirectional column factor counter.... | 07/18/2000 |
| 6081853 | Method for transferring burst data in a microprocessor A method for burst transferring of data in a processing system is provided. The processing system has a data bus width of W bytes (W even) and a cache line length of L bytes (L even). The cache line has L/W banks, the lowermost bank being in an odd positi... | 06/27/2000 |
| 6081480 | Semiconductor integrated circuit Writing of unwanted data is inhibited if signals other than a required number of clocks are applied for a program for a memory. A program control circuit 1 delivers a write-starting instruction. A clock number-detecting circuit 2 for detecting a given number o... | 06/27/2000 |
| 6081472 | Cell refresh circuit of memory device A cell refresh circuit of a memory device is provided that prevents deterioration in EPROM programmed data. The cell refresh circuit compensates for the loss of programmed data by reprogramming the programmed data in the EPROM after a predetermined time. ... | 06/27/2000 |
| 6078637 | Address counter test mode for memory device A memory having a circuit including a built-in address counter with a test mode. The address counter may be used to generate the memory array addressing for the different array test patterns. The circuit may comprise a logic circuit and a counter circuit.... | 06/20/2000 |
| 6078636 | Counter circuit and semiconductor memory having counter circuit as address counter circuit A counter circuit, which may be on a semiconductor integrated circuit, that is applicable to both a linear sequence and an interleave sequence and is capable of setting a burst length at 1, 2, 4, 8, or 2n in both sequences. The burst length of ... | 06/20/2000 |
| 6078525 | Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row... | 06/20/2000 |
| 6078548 | CPU capable of modifying built-in program codes thereof and method for the same A CPU includes a program counter, a ROM, a RAM with a size smaller than the ROM, a special instruction detecting circuit and a multiplexer. A special instruction is written in an address of the RAM corresponding to the memory address, where the program co... | 06/20/2000 |
| 6078516 | Ferroelectric memory A memory device has a ferroelectric memory cell block, which is connected via an input/output latch buffer to a data input terminal. The memory device also has a writing period forming circuit that forms a predetermined number of writing periods when writ... | 06/20/2000 |
| 6070203 | Circuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOS An efficient design to generate a programmable almost empty or programmable almost full flags. The present invention accomplishes this by efficiently evaluating the read count minus write count plus a user programmed offset being greater than or equal to ... | 05/30/2000 |
| 6069829 | Internal clock multiplication for test time reduction A circuit is designed with a clock circuit (215, 217) coupled to receive a control signal having a first logic state and a second logic state. The clock circuit produces a first clock signal (CLK) response to the first logic state and a second clock signa... | 05/30/2000 |
| 6069830 | Circuit and method for sensing memory cell having multiple threshold voltages A circuit and method for sensing a memory cell having a plurality of threshold voltages is provided that implements a low power and voltage sensing operation and reduces a multiple level memory cell size by reducing the size of the circuit. The circuit in... | 05/30/2000 |
| 6067273 | Semiconductor memory burst length count determination detector The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is co... | 05/23/2000 |
