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| Number | Title | Issue Date |
| 6381193 | Apparatus for externally timing high voltage cycles of non-volatile memory system An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the ... | 04/30/2002 |
| 6373758 | System and method of operating a programmable column fail counter for redundancy allocation The present invention includes a system and a methodology for eliminating faulty memory cells in a memory array with replacement columns of memory cells and replacement rows of memory cells. The individual memory cells are checked to ensure that each is o... | 04/16/2002 |
| 6373785 | Semiconductor memory device A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterin... | 04/16/2002 |
| 6366634 | Accelerated carry generation An address binary counter for an interleaved having an array of memory cells being divided into a first bank of memory cells and a second bank of memory cells includes as many stages as the bits that may be stored in the memory cells of a row of one of th... | 04/02/2002 |
| 6363031 | Circuit, architecture and method for reducing power consumption in a synchronous integrated circuit An apparatus comprising a circuit configured to automatically generate a sleep signal upon detecting that one or more chip select signals has been in a first state for a predetermined number of clock cycles.... | 03/26/2002 |
| 6363032 | Programmable counter circuit for generating a sequential/interleave address sequence A programmable counter circuit for use in semiconductor memories for generating both sequential and interleave address sequences for block data accesses is disclosed. The output and complementary output of the counter for a previous bit are multiplexed to... | 03/26/2002 |
| 6353574 | Semiconductor memory device having pipe register operating at high speed A pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global... | 03/05/2002 |
| 6351833 | Address generator An address generator is provided for generating addresses needed to read out data from a memory. The address generator includes a first and a second latch circuits, and a first counter connected to each of the first and the second latch circuits. The addr... | 02/26/2002 |
| 6351434 | Synchronous counter for electronic memories A memory counter circuit includes a plurality of mutually connected counter stages, an internal address bus interfaced with each one of the counter stages for sending an external address signal to each one of the counter stages, a circuit for loading the ... | 02/26/2002 |
| 6345008 | Fast reprogrammable FIFO status flags system A reprogrammable FIFO status flags system for determining the status of a FIFO memory having a storage capacity (depth) D generates a pair of FIFO status flags, PAF (Programmable Almost Full) and PAE (Programmable Almost Empty) that can be reprogrammed mu... | 02/05/2002 |
| 6345002 | RAS monitor circuit and field memory using the same A field memory includes a DRAM core, a processor that generates and supplies a RAS control signal to the DRAM core, and a RAS cycle monitor circuit. The RAS cycle monitor circuit includes a counter circuit that counts the number of cycles of a RAS control... | 02/05/2002 |
| 6343355 | Sequence controller capable of executing different kinds of processing at respective periods A sequence controller includes a sequencer to which a basic clock is applied. The sequencer sequentially generates at a period of 125 μsec address signals for reading statements to be executed at a period of 125 μsec and one block of statements to be ex... | 01/29/2002 |
| 6341097 | Selective address space refresh mode A method and system of refreshing a DRAM having a multitude of successive wordlines. The method comprises the step of starting a refresh cycle, and this starting step includes the steps of (I) counting the wordlines one at a time in succession, (ii) refre... | 01/22/2002 |
| 6339809 | Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffers A buffer access control circuit to access a buffer which is divided into an upper buffer and a lower buffer which are assigned the same address and a memory unit including the buffer access control circuit. The buffer access control circuit includes latch... | 01/15/2002 |
| 6337810 | Semiconductor memory device and method for reading data The provision of a semiconductor memory device for which access times in burst mode can be improved with no increase in the chip surface area and with no increase in power consumption. A latch pulse selection circuit 6 uses a control signal CA0T to output... | 01/08/2002 |
| 6333892 | Synchronous semiconductor memory device capable of selecting column at high speed A command decoder receives an externally supplied command independently of an internal clock signal, decodes the command, generates a column access mode instruction signal, and activates a column address activation signal when the internal clock signal ri... | 12/25/2001 |
| 6333888 | Semiconductor memory device A semiconductor memory device capable of normally executing a refresh counter test with simplified circuit configurations and wiring is provided. According to the semiconductor memory device of the present invention, column decoders of all banks are activ... | 12/25/2001 |
| 6327209 | Multi stage refresh control of a memory device A memory device is disclosed which includes a refresh control circuit which responds to a refresh request command and performs at least two refresh operations. In the first refresh operation, a first word line is selected and memory cells associated with ... | 12/04/2001 |
| 6327216 | Full page increment/decrement burst for DDR SDRAM/SGRAM A graphics subsystem having a dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM), which has a full-page increment/decrement burst mode. In one embodiment, the DDR SDRAM/SGRAM includes a m... | 12/04/2001 |
| 6324115 | Semiconductor memory device with burst mode access A data sensing control circuit according to the present invention is provided in a semiconductor memory device with a burst access mode. The data sensing control circuit generates sensing control signals for data sensing operation by use of a transition i... | 11/27/2001 |
| 6310824 | Integrated memory with two burst operation types The memory has a bidirectional address counting unit C1; S, which performs a counting operation for the purpose of generating internal column addresses from an external column address A7 . . . 0. In this case, the counting direction is dependent on the bu... | 10/30/2001 |
| 6301159 | 50% EXE tracking circuit A tracking circuit is provided for performing an erase verify/erase operation so as to prevent over-erasure in an array of EEPROM memory cells. A binary counter is used to count the number of erase pulses during a normal erase verify/erase operation. Coun... | 10/09/2001 |
| 6298006 | Method and apparatus to automatically determine the size of an external EEPROM The present invention automatically determines the size of an EEPROM in a circuit. A controller is connected to the EEPROM with both a "data to" the EEPROM connection and a "data from" the EEPROM connection. The controller begins to send logical low addre... | 10/02/2001 |
| 6282148 | Apparatus for externally timing high voltage cycles of non-volatile memory system An apparatus which allows the pulse duration of the high voltage pulses used in the programming and erase operations of a non-volatile memory system to be determined by an external timing signal instead of the internal timer normally used. Control of the ... | 08/28/2001 |
| 6278652 | Input initial stage circuit for semiconductor memory In a semiconductor memory which includes an input initial stage circuit receiving an external clock for generating an internal clock and an internal circuit operating on the basis of the internal clock, the input initial stage circuit comprises a first in... | 08/21/2001 |
| 6275416 | Pulse generator circuit, particularly for non-volatile memories A pulse generator circuit for non-volatile memories, is disclosed, including a circuit for determining the instant at which a pulse for incrementing a counter of the memory is generated and generating an increment pulse duration start signal; a circuit fo... | 08/14/2001 |
| 6272065 | Address generating and decoding circuit for use in burst-type random access memory device having a double data rate, and an address generating method thereof Disclosed is a burst-type random access memory device with a double data rate scheme, in which at least two data is inputted/outputted to/from the memory device during a clock cycle. In the burst-type random access memory device, a first address generator... | 08/07/2001 |
| 6262916 | Non-volatile semiconductor memory device capable of pre-conditioning memory cells prior to a data erasure In a non-volatile semiconductor memory device, a binary counter is connected to a most significant bit portion of an address counter for successively generating addresses of rows of a memory cell array. The binary counter forcibly selects one of spare row... | 07/17/2001 |
| 6262938 | Synchronous DRAM having posted CAS latency and method for controlling CAS latency A synchronous DRAM (SDRAM) having a posted column access strobe (CAS) latency and a method of controlling CAS latency are provided. In order to control a delay time from the application of a CAS command and a column address to the beginning of memory, rea... | 07/17/2001 |
| 6259651 | Method for generating a clock phase signal for controlling operation of a DRAM array A method and structure for handling the refresh of a DRAM array so that the refresh has no effect on the external access. A system clock signal initiates activation and deactivation of elements of the DRAM array using a sequencer which subdivides each sys... | 07/10/2001 |
| 6259649 | Semiconductor memory circuit layout capable of reducing the number of wires The present invention relates to a semiconductor memory circuit capable of reducing the number of routes to decrease the area of a chip. In a construction of a synchronous semiconductor memory circuit with a LOC architecture in accordance with the present... | 07/10/2001 |
| 6259646 | Fast accessing of a memory device Improved methods and structures are provided that allow for fast access of a memory device. Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circu... | 07/10/2001 |
| 6256259 | Delay-locked loop with binary-coupled capacitor A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the... | 07/03/2001 |
| 6249481 | Semiconductor memory device A semiconductor memory device comprises a memory cell group comprising a plurality of memory cells arranged in matrix; a specification circuit for specifying sequentially memory cells addressed by consecutive addresses in the memory cells, and for enterri... | 06/19/2001 |
| 6246603 | Circuit and method for substantially preventing imprint effects in a ferroelectric memory device A method and circuit are disclosed for maintaining stored data within a ferroelectric memory device. The circuit includes a first circuit for selectively logically inverting the data in the ferroelectric memory device. A second circuit enables the first c... | 06/12/2001 |
| 6246630 | Intra-unit column address increment system for memory A system and method is disclosed herein for providing column address increment pipelining within a single physically contiguous storage array, such as a left or a right unit of a double unit. Thereby, a multiple bank arrangement is provided within a doubl... | 06/12/2001 |
| 6246619 | Self-refresh test time reduction scheme A circuit for a DRAM is described which, when in test mode, notifies a tester when the self-refresh operation of a dynamic random access memory (DRAM) reaches various stages of completion. By signaling the tester when, i.e., 1/8, 1/4, 1/2, etc. of the sel... | 06/12/2001 |
| 6243777 | Circuit for preventing bus contention A circuit for controlling the data transmissions among two devices capable of transmitting information, via an output buffer, over a bus, so as to prevent bus contention, is comprised of a first device enabled circuit for generating a first device enabled... | 06/05/2001 |
| 6229759 | Semiconductor memory burst length count determination method The present invention is directed to a circuit for detecting the end of a burst count in a semiconductor memory device. The circuit is responsive to a plurality of burst counter output bits and a plurality of burst length selection bits. The circuit is co... | 05/08/2001 |
| 6222793 | Memory devices having a restore start address counter Embodiments of the present invention may provide methods of controlling a memory device and memory devices including a memory array having an internal address input which specifies a location in the memory array accessed during read operations and write o... | 04/24/2001 |
