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Combination Beverage Container and Spittoon
A combination beverage container and spittoon includes a bottom portion including outer wall and a first inner wall defining a spittoon space.
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| Number | Title | Issue Date |
| 7872941 | Nonvolatile memory device and method of operating the same A nonvolatile memory device comprises a page buffer unit, first to kth logic combination units, and a control unit. The page buffer unit includes first to Nth page buffer blocks. N and k are natural numbers. Each of the first to Nth ... | 01/18/2011 |
| 7508732 | Multi-bit flash memory device including memory cells storing different numbers of bits A flash memory device comprises an array of memory cells capable of storing different numbers of bits per cell. A page buffer circuit for the flash memory device comprises a plurality of page buffers, each operating during programming, erasing, and reading operation... | 03/24/2009 |
| 7400531 | Semiconductor integrated circuit device A semiconductor integrated circuit device has a page buffer, several memory cells to which data is written in accordance with write data stored in the page buffer, and an accumulating counter. The accumulating counter accumulates and stores a number of program loops... | 07/15/2008 |
| 7400549 | Memory block reallocation in a flash memory device A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coup... | 07/15/2008 |
| 7391632 | Apparatus of selectively performing fast hadamard transform and fast fourier transform, and CCK modulation and demodulation apparatus using the same A Fast Fourier Transform (FFT) apparatus for selectively performing Fast Hadamard transform (FHT), and a complementary code keying (CCK) modulation/demodulation apparatus using the same. An OFDM module and CCK module are integrated as one module having lower complex... | 06/24/2008 |
| 7369432 | Method for implementing a counter in a memory with increased memory efficiency A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the fir... | 05/06/2008 |
| 7336543 | Non-volatile memory device with page buffer having dual registers and methods using the same A non-volatile memory device with a page buffer having dual registers includes a memory cell array, a selector circuit and a page buffer circuit, the selector circuit being coupled to an exterior data line, the page buffer circuit including a first register and a se... | 02/26/2008 |
| 7313028 | Method for operating page buffer of nonvolatile memory device A method for operating a page buffer of a nonvolatile memory device reduces errors while transferring data between latches and shortens a copy-back programming time. The copy-back program is carried out using one among several latch circuits included in the page buf... | 12/25/2007 |
| 7310284 | Page access circuit of semiconductor memory device A page access circuit of a semiconductor memory device comprises a page address detecting unit configured to detect transition of a page address in response to a page address control signal so as to generate a page address detecting signal, a page control unit confi... | 12/18/2007 |
| 7310275 | Non-volatile memory device and method for operation page buffer thereof A non-volatile memory device includes a memory cell array including memory cells, each memory cell being defined at an intersection of a word line and a bit line. A page buffer is coupled to the memory cell array via a sensing line. The page buffer comprises a first... | 12/18/2007 |
| 7215720 | Method for compensating baseline wander of a transmission signal and related circuit A method for compensating a baseline wander of a transmission signal and related circuit are provided. The transmission signal includes a plurality of first pulses and a plurality of second pulses for representing digital data coded in the transmission signal. The m... | 05/08/2007 |
| 7212426 | Flash memory system capable of inputting/outputting sector data at random A flash memory system capable of inputting/outputting data in units of sectors at random. The flash memory system includes a flash memory (a cell array), a buffer memory, a random data input/output circuit, and a control circuit. The random data input/output circuit... | 05/01/2007 |
| 7184362 | Page access circuit of semiconductor memory device A page access circuit of a semiconductor memory device is normally operated even when a page address toggles at any timing in a page mode. The page access circuit comprises an address buffer, a column control unit, a page control unit, a pre-active unit and a precha... | 02/27/2007 |
| 7164523 | Image exposure system An image exposure system is formed by a spatial light modulator element comprising a number of two-dimensionally arranged pixel portions each modulating light projected thereon, a light source which projects light onto the spatial light modulator element and an imag... | 01/16/2007 |
| 7149130 | Page buffer circuit of flash memory device with reduced consumption power A page buffer circuit of a flash memory device has small consumption power. The page buffer circuit utilizes different voltages are supplied to the latch circuits in the standby and normal modes to reduce consumption power in the standby mode. ... | 12/12/2006 |
| 7133324 | Synchronous dynamic random access memory devices having dual data rate 1 (DDR1) and DDR2 modes of operation and methods of operating same A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM. | 11/07/2006 |
| 7126688 | Microarray scanning Methods and apparatus for scanning of a microarray to provide an image of the microarray are disclosed. Data related to change in polarization state of a scanning light beam for individual points or lines or other portion of the microarray are collected and processe... | 10/24/2006 |
| 7079448 | Word-programmable flash memory The present invention relates to a memory in integrated circuit comprising a central Flash-type memory comprising memory cells forming pages, a buffer memory capable of storing binary words, and a sequencer for executing an instruction for saving, in a target page o... | 07/18/2006 |
| 7042792 | Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays A multi-port memory cell includes a first SRAM element having a first pair of access transistors electrically coupled to a pair of FIFO write bit lines. A second dual-port SRAM element is also provided. This second dual-port SRAM element has a second pair of access ... | 05/09/2006 |
| 7016226 | Semiconductor memory device for storing multivalued data Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a sec... | 03/21/2006 |
| 6992943 | System and method for performing partial array self-refresh operation in a semiconductor memory device Systems and methods for performing a PASR (partial array self-refresh) operation wherein a refresh operation for recharging stored data is performed on a portion (e.g., ½ ¼, ⅛, or 1/16) of one or more selected memory banks comprising a cell array in a semiconduc... | 01/31/2006 |
| 6990044 | Composite memory device The present invention relates to a composite memory device comprising first through third memory devices, a memory bus, and first through third memory controllers. The first memory device is an asynchronous memory device, the second memory device is a synchronous me... | 01/24/2006 |
| 6950350 | Configurable pipe delay with window overlap for DDR receive data A system for maximizing set up and hold times for data reads from a DDR memory device. The system adjusts timing of a strobe from a DDR memory device and converts data from the DDR memory device into a single-data-rate data. The timing adjustment is preferably contr... | 09/27/2005 |
| 6944093 | Semiconductor memory device A semiconductor memory device is provided, which comprises a memory array comprising a plurality of memory cells, a page buffer section for temporarily storing data to be written into the memory array, and a masking section for masking at least a portion of data rea... | 09/13/2005 |
| 6934074 | Optical element and manufacturing method thereof An optical element has of a set a plurality of three-dimensional cells. A specific amplitude and a specific phase are defined in each individual cell. Each cell has a concave part formed by hollowing a part having an area corresponding to the specific amplitude by a... | 08/23/2005 |
| 6914704 | Obliquity correction system Disclosed are methods of producing obliquity corrected light beams, and holographic recording and retrieval systems that utilize a obliquity corrected reference beam. The obliquity correction is accomplished using off-center lenses. ... | 07/05/2005 |
| 6839285 | Page by page programmable flash memory An integrated circuit memory includes a FLASH memory including a circuit for recording a word presented on its input without the possibility of recording simultaneously several words in parallel. The integrated circuit memory may include a buffer memory with a suffi... | 01/04/2005 |
| 6807098 | Nonvolatile semiconductor memory with a programming operation and the method thereof The invention provides a method of programming in a nonvolatile semiconductor memory device, having a plurality of memory cell strings connected to a plurality of bitlines and constructed of a plurality of memory cell transistors whose gates are coupled to a plurali... | 10/19/2004 |
| 6785190 | Method for opening pages of memory with a single command An efficient invention for opening two pages of memory for a DRAM are discussed. ... | 08/31/2004 |
| 6781879 | Nonvolatile semiconductor memory with a page mode A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in... | 08/24/2004 |
| 6745279 | Memory controller A memory controller is disclosed, in which upon receipt of an access request from a device, the memory controller activates a page designated by a row address of a first bank at a predetermined memory cycle, based on the access request. After that, before the read a... | 06/01/2004 |
| 6724682 | Nonvolatile semiconductor memory device having selective multiple-speed operation mode Disclosed is a nonvolatile semiconductor memory device having selective multiple-speed operation modes selected by simple options. The nonvolatile semiconductor memory device includes a memory cell array formed of a plurality of cell array blocks each having a plura... | 04/20/2004 |
| 6724670 | Shared redundancy for memory having column addressing A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory arrays, fuse... | 04/20/2004 |
| 6683817 | Direct memory swapping between NAND flash and SRAM with error correction coding Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specific design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage ... | 01/27/2004 |
| 6675269 | Semiconductor device with memory controller that controls page mode access A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performe... | 01/06/2004 |
| 6587934 | Memory controller and data processing system A memory controller and data processor have their operation mode switched from the page-on mode for high-speed access to a same page to the page-off mode in response to consecutive events of access to different pages, so that the memory access is performe... | 07/01/2003 |
| 6496446 | Semiconductor memory device having burst readout mode and data readout method A semiconductor memory having burst mode operation includes a memory cell array, a sense amplifier circuit determining data of memory cells, a latch circuit having first and second latch groups and latching data of a sense amplifier, an enable circuit pro... | 12/17/2002 |
| 6480429 | Shared redundancy for memory having column addressing A shared redundancy prefetch scheme to provide a reduced number of fuses. DDR SDRAMs allow burst addressing at various burst lengths. DDR SDRAMs generally implement LEFT and RIGHT segment column addressing. In DDR SDRAMs which implement redundant memory a... | 11/12/2002 |
| 6477101 | Read-ahead electrically erasable and programmable serial memory A serial input/output memory is able to read data in the memory upon reception of a partial read address in which there are N least significant bits lacking to form a complete address. The read-ahead step includes: simultaneously reading the P first bits ... | 11/05/2002 |
| 6449209 | Semiconductor memory device comprising more than two internal banks of different sizes A semiconductor memory device includes a plurality of internal banks of different sizes. The internal banks are suitable for and correspond to the memory needs of a plurality of master devices. Master devices are assigned banks having sizes matched to the... | 09/10/2002 |
