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| Number | Title | Issue Date |
| 7302029 | Counting circuit for controlling an off-chip driver and method of changing an output current value of the off-chip driver using the same Provided is a counting circuit for controlling an off-chip driver and method of changing a DC output current value of the off-chip driver using the same in accordance with variations of processing characteristics with PMOS and NMOS in the state of wafer level. The c... | 11/27/2007 |
| 7301384 | Multimode, uniform-latency clock generation circuit A multimode, uniform-latency clock generation circuit (CGC) is described herein. In one example, the multimode, uniform-latency CGC generates a pulse clock signal via a clock generation path responsive to a clock chopping signal being active and generates a phase cl... | 11/27/2007 |
| 7301385 | Methods and apparatus for managing clock skew An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal,... | 11/27/2007 |
| 7301971 | Method and apparatus for continuous synchronization of a plurality of asynchronous data sources An apparatus and method for continuous synchronization of a pair of independently clocked asynchronous data streams (100, 101) consisting of raster data from independent imaging acquisition systems comprises a means for acquiring individual rasters from a fir... | 11/27/2007 |
| 7298669 | Tri-mode clock generator to control memory array access A clock generator is provided that is compatible with both DDR1 and DDR2 applications. The internal YCLK signal is turned on only when an active read or write occurs on the integrated circuit memory, even though the main chip clock is always running. A circuit block... | 11/20/2007 |
| 7298670 | Integrated circuit with analog or multilevel storage cells and user-selectable sampling frequency Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage l... | 11/20/2007 |
| 7298662 | Semiconductor device with power down arrangement for reduce power consumption A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both ... | 11/20/2007 |
| 7298667 | Latency control circuit and method of latency control In one embodiment, a latency circuit generates the latency signal based on CAS latency information and read information. For example, the latency circuit may include a clock signal generating circuit generating a plurality of transfer signals and generating a plural... | 11/20/2007 |
| 7298668 | Semiconductor memory module with bus architecture A semiconductor memory module, which is formed as an FBDIMM memory module, for example, has a planar design. In the 2R×4 configuration, semiconductor components are arranged in two rows on a top side of a module board and semiconductor memory components are likewis... | 11/20/2007 |
| 7295057 | Methods and apparatus for characterizing electronic fuses used to personalize an integrated circuit An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the f... | 11/13/2007 |
| 7295488 | Apparatus and methods for generating a column select line signal in semiconductor memory device An apparatus for generating a column select line signal in a semiconductor memory device includes a column select line signal generator configured to generate a column select line signal in response to a column select line enable signal. The column select line signa... | 11/13/2007 |
| 7295489 | Method and circuit for writing double data rate (DDR) sampled data in a memory device A method and circuit for sampling and writing data in a double data rate (DDR) memory device, capable of securing sufficient setup and hold margins regardless of the operation frequency. Transferring first and second sampled input data to a first path using a first ... | 11/13/2007 |
| 7296110 | Memory system and data channel initialization method for memory system Provided is a memory system and a method that can initialize a data channel at a high speed without the need to increase the number of pins in a semiconductor memory device, and not requiring a circuit to perform an initialization. The memory system includes a memor... | 11/13/2007 |
| 7296124 | Memory interface supporting multi-stream operation A memory device includes one or more memory arrays and an interface controller for exchanging memory contents data with a semiconductor device over a communication link. The exchanging of data occurs within sequential transactions. Each transaction is associated wit... | 11/13/2007 |
| 7296129 | System, method and storage medium for providing a serialized memory interface with a bus repeater A packetized cascade memory system including a plurality of memory assemblies, a memory bus including multiple segments, a bus repeater module and a segment level sparing module. The bus repeater module is in communication with two or more of the memory assemblies v... | 11/13/2007 |
| 7296173 | Semiconductor integrated circuit A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input te... | 11/13/2007 |
| 7294998 | Timing generation circuit and semiconductor test device having the timing generation circuit A timing generation circuit can increase a maximum delay amount without changing the configuration of a timing memory. The timing generation circuit includes: a timing memory (TMM) 10 containing predetermined timing data; a plurality of down counters 20 | 11/13/2007 |
| 7292499 | Semiconductor device including duty cycle correction circuit A duty cycle correction (DCC) circuit receives first and second clock signals and outputs a duty cycle adjusted clock signal, and a control circuit detects a process variation and controls respective slew rates of the first and second clock signals based on the dete... | 11/06/2007 |
| 7293123 | Asymmetric data path media access controller A method and apparatus for maintaining data throughput in a data element includes receiving a clock and a first plurality of instances of data having a first width on an input, sampling consecutive ones of instances of the data having the first width at consecutive ... | 11/06/2007 |
| 7292500 | Reducing read data strobe latency in a memory system A read activity detector circuit for use in a random access memory array includes a plurality of synchronizer circuits operative to receive a plurality of respective reference clock signals having a frequency that is substantially the same as a core reference clock ... | 11/06/2007 |
| 7292454 | System and method for optimizing printed circuit boards to minimize effects of non-uniform dielectric A system and method for minimizing the effects of non-uniform dielectric properties includes forming traces on printed circuit boards (PCB) where the fibers within the printed circuit boards are non-rectangular with respect to the rectangular edges of the circuit bo... | 11/06/2007 |
| 7292480 | Memory card having buffer memory for storing testing instruction A memory card (1) includes an electrically rewritable non-volatile memory (4), a data processor (3) having a function of executing instructions, and managing the allocation of file data in the non-volatile memory, an interface control circuit ( | 11/06/2007 |
| 7292486 | Methods and circuits for latency control in accessing memory devices Methods of providing a delay for access to a memory device can include adjusting a delay for access to data during memory operations based on at least one parameter associated with a reduction in voltage levels provided to the memory. Related circuits are also discl... | 11/06/2007 |
| 7292490 | System and method for refreshing a DRAM device The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh ... | 11/06/2007 |
| 7293151 | Memory system and method for transferring data therein A memory system is functionally designed so that, despite operation without an error correction device, memory chips of a memory module that are actually provided for error correction are concomitantly used for the data transfer. A control device is configured to re... | 11/06/2007 |
| 7293190 | Noisy clock test method and apparatus A clock filter for use in filtering an external clock signal to create an internal clock signal for use by an electronic device is provided. The clock filter receives the external clock signal and sets the internal clock signal high when the external clock signal is... | 11/06/2007 |
| 7290117 | Memory having increased data-transfer speed and related systems and methods A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes... | 10/30/2007 |
| 7290158 | Method of controlling data transfer within a semiconductor integrated circuit based on a clock sync control signal A semiconductor integrated circuit device comprises an internal bus, a plurality of internal modules connected to the internal bus and including a main module performing a predetermined function, and a clock generating unit generating a reference clock and a clock s... | 10/30/2007 |
| 7289347 | System and method for optically interconnecting memory devices A memory device includes a semiconductor substrate in which memory circuitry has been fabricated. An address converter and a control signal converter are coupled to an address decoder and control logic, respectively. The address and control converters are operable t... | 10/30/2007 |
| 7289385 | Bank selection signal control circuit for use in semiconductor memory device, and bank selection control method Memory bank selection control circuits and methods are provided which improve the data sensing margin for data sense amplifiers in a multi-bank semiconductor memory structure. In one aspect, a bank selection signal control circuit includes a bank switch control unit... | 10/30/2007 |
| 7289373 | High performance memory device A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected ... | 10/30/2007 |
| 7289377 | Internal voltage generator capable of regulating an internal voltage of a semiconductor memory device An internal voltage generator maintains stable level of an internal voltage without increasing physical area. The internal voltage generator includes an active level detector for detecting a level of an internal voltage by comparing the level of the internal voltage... | 10/30/2007 |
| 7289383 | Reducing the number of power and ground pins required to drive address signals to memory modules One embodiment of the present invention provides a system that reduces the number of power and ground pins required to drive address signals to system memory. During operation, the system receives address signals associated with a memory operation from a memory cont... | 10/30/2007 |
| 7289379 | Memory devices and methods of operation thereof using interdependent sense amplifier control A memory device includes a control circuit configured to disable a local input/output line sense amplifier responsive to a global input/output line sense amplifier enable signal. The device may further include a column select gate configured to control transfer of d... | 10/30/2007 |
| 7289384 | Method for writing to multiple banks of a memory device In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number... | 10/30/2007 |
| 7287115 | Multi-chip package type memory system A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, an... | 10/23/2007 |
| 7287119 | Integrated circuit memory device with delayed write command processing An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to ... | 10/23/2007 |
| 7287143 | Synchronous memory device having advanced data align circuit A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in resp... | 10/23/2007 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7286432 | Temperature update masking to ensure correct measurement of temperature when references become unstable Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature... | 10/23/2007 |
