Did You Know...
...that in 1800 ether was first used by partyers as a fun diversion? Sniffing the gas led to hilarious and raucous laughter as people watched each other become more and more intoxicated and silly. Several doctors independently realized the value ether would have to anesthetize surgery patients. Of those who claimed rights to the "discovery," none had a happy ending. One had a seizure and died defending his rights. Another spent his life in an asylum because he had been denied acclaim. A third became addicted to chloroform and, in a New York City jail, he soaked a cloth in the drug, severed an artery and bled to death.
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| Number | Title | Issue Date |
| 7277354 | Apparatus and method for updating data in a dual port memory A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an add... | 10/02/2007 |
| 7277357 | Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter con... | 10/02/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7276944 | Clock generation circuit and clock generation method A clock generation circuit and a clock generation method are provided, which are spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal. An input divider unit 70 divides an input clock signal CLKR by... | 10/02/2007 |
| 7276946 | Measure-controlled delay circuits with reduced phase error Measure-controlled delay (MCD) circuits include a measure circuit and sample circuit for synchronizing an output clock to an input clock. In response to triggering of the measure circuit, sample circuits sample outputs of a measure delay array. Sample reset logic pr... | 10/02/2007 |
| 7277996 | Modified persistent auto precharge command protocol system and method for memory devices A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disab... | 10/02/2007 |
| 7277334 | Method and apparatus for synchronization of row and column access operations A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising... | 10/02/2007 |
| 7276955 | Circuit and method for stable fuse detection A fuse state detection circuit is comprised of a first fuse element, a second fuse element, and an output for carrying an output signal, the output signal represents a first logic state when the first fuse element is blown and the second fuse element is unblown and ... | 10/02/2007 |
| 7278078 | Built-in self-test arrangement for integrated circuit memory devices An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (410) that stores test algorithm instructions. A Rom logic circuit (410) receives an instruction read f... | 10/02/2007 |
| 7277988 | System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a... | 10/02/2007 |
| 7278045 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 10/02/2007 |
| 7278033 | Method and a system for determining the power consumption in connection with an electronic device, and an electronic device The present invention relates to a method and a system for determining the power consumption in an electronic device, to which a peripheral device is connected, to which the power is supplied from the electronic device. At least a first maximum value and a second ma... | 10/02/2007 |
| 7274200 | Semiconductor circuit, method of monitoring semiconductor-circuit performance, method of testing semiconductor circuit, equipment for testing semiconductor circuit, and program for testing semiconductor circuit A semiconductor circuit is disclosed, including a DLL circuit for supplying a desired signal-delay amount. The DLL circuit includes detecting means for detecting variations of a signal-delay amount, and delay-amount control means for generating a delay-amount contro... | 09/25/2007 |
| 7274228 | Method and apparatus for digital phase generation at high frequencies An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitu... | 09/25/2007 |
| 7274583 | Memory system having multi-terminated multi-drop bus Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first im... | 09/25/2007 |
| 7274590 | Random access memory with stability enhancement and early read elimination A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or g... | 09/25/2007 |
| 7274606 | Low power chip select (CS) latency option A system and method to reduce standby currents in input buffers in an electronic device (e.g., a memory device) is disclosed. The input buffers may be activated or deactivated by the state of a chip select (CS) signal. In case of a memory device, the active and prec... | 09/25/2007 |
| 7274605 | Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM A synchronous double-data-rate semiconductor memory device is adapted to receive write data on both the rising and falling edges of a data strobe signal derived from an externally-applied system clock. In the write path circuitry for each data pin of the device, adj... | 09/25/2007 |
| 7275172 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 09/25/2007 |
| 7274620 | Semiconductor memory device The present invention for preventing a data error by satisfying specifications of tHD and tCBPH is provided. The semiconductor memory device having an enough margin for a write/read operation includes a pre-charging block for performing a pre-charging operation base... | 09/25/2007 |
| 7275135 | Hardware updated metadata for non-volatile mass storage cache An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be m... | 09/25/2007 |
| 7274607 | Bitline exclusion in verification operation Methods and apparatuses for disabling a bad bitline for verification operations, and for determining whether a programming operation have failed, include setting a bitline disable latch for a bad bitline, and inhibiting operation of a program latch if the bitlines i... | 09/25/2007 |
| 7272682 | Memory hub bypass circuit and method A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurali... | 09/18/2007 |
| 7272069 | Multiple-clock controlled logic signal generating circuit A multiple-clock controlled logic signal generating circuit is proposed, which is designed for use to generate a logic signal during specified periods with reference to multiple clock signals; and which is characterized by the use of a set of switching modules to sw... | 09/18/2007 |
| 7272056 | Data output controller in semiconductor memory device and control method thereof A data output controller of a high-speed memory device and a method therefore. The data output controller includes a first section for detecting a unit delay multiple of an external clock signal based on the external clock signal and a delay circuit of the external ... | 09/18/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
| 7272807 | Determining equivalent waveforms for distorted waveforms An equivalent waveform for a distorted waveform used in timing and signal integrity analysis in the design of an integrated circuit is automatically generated. The equivalent waveform is produced by calculating the transition quantity of a first non-distorted wavefo... | 09/18/2007 |
| 7272054 | Time domain bridging circuitry for use in determining output enable timing A method and circuitry for alleviating the adverse effect of variable read decode propagation delays and variable output circuitry propagation delays on the read latency, and specifically for generating output enable signals at an appropriate time in light of such v... | 09/18/2007 |
| 7272742 | Method and apparatus for improving output skew for synchronous integrated circuits A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffer... | 09/18/2007 |
| 7272030 | Global bit line restore timing scheme and circuit A domino SRAM array restore pulse generation system launches the work decode line by the same local clock as the restore pulse, thus eliminating any race issues with the word line select. This system allows the global bit select (or column select) to have fast activ... | 09/18/2007 |
| 7272055 | Method and apparatus for timing adjustment A strobe signal from a memory is delayed through delay circuits of a strobe delay selection section, thus obtaining a plurality of delayed strobe signals. A strobe latch section produces check data in synchronism with each of the delayed strobe signals, and a system... | 09/18/2007 |
| 7272071 | Systems and methods that employ inductive current steering for digital logic circuits The present invention provides systems and methods that utilize inductive current steering to improve logic circuit performance by mitigating propagation delays associated with conventional transistor current steering. The system and methods employ RF transformers, ... | 09/18/2007 |
| 7272063 | Memory with a temperature sensor, dynamic memory and memory with a clock unit and method of sensing a temperature of a memory Methods and apparatus for determining a temperature of a memory device. A memory device includes a memory array, a temperature configured to measure a temperature of the device and an evaluating circuit configured to receive a signal representative of the temperatur... | 09/18/2007 |
| 7268531 | Apparatus for improving stability and lock time for synchronous circuits Delay-locked loops, signal locking methods and devices and system incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively cou... | 09/11/2007 |
| 7269082 | Chip enable control circuit, memory control circuit, and data processing system A CE control circuit includes a CE signal generating circuit which sets a CE signal to an enable level when bringing the memory to an operable state or sets the CE signal to a disable level when bringing the memory to a low power consumption state, and a reference v... | 09/11/2007 |
| 7268601 | Delay locked loop and clock generation method thereof A semiconductor device for correcting a duty of a clock signal includes a first clock buffer for receiving an external clock signal through a non-inverting terminal of the first clock buffer and for receiving an external clock bar signal through an inverting termina... | 09/11/2007 |
| 7269075 | Method and apparatus for simultaneous differential data sensing and capture in a high speed memory A differential data sensing and capture circuit, includes a differential input stage circuit for receiving respective ones of said differential data signals and having first and second output nodes. A latch element is provided, having first and second complementary ... | 09/11/2007 |
| 7269093 | Generating a sampling clock signal in a communication block of a memory device A method generates a sampling clock signal in a communication block of a memory device having a plurality of communication blocks which are distributed in the memory device. The method includes receiving an input clock signal in the communication block, generating, ... | 09/11/2007 |
| 7269754 | Method and apparatus for flexible and programmable clock crossing control with dynamic compensation A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch com... | 09/11/2007 |
| 7269094 | Memory system and method for strobing data, command and address signals A memory system couples command, address or write data signals from a memory controller to a memory device and read data signals from the memory device to the memory controller. A respective strobe generator circuit in each of the memory controller and the memory de... | 09/11/2007 |
