Celebrity Inventors
Comic actor Danny Kaye received patent D166,807 for the co-design of "Blowout Toy or the Like". It's similar to one of those toys that unravels when you blow into at a birthday party except Kaye's has three blowouts going in different directions, not just one.
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| Number | Title | Issue Date |
| 4129793 | High speed true/complement driver A high speed true/complement driver circuit is disclosed wherein the time interval between the address and memory select pulses are minimized by utilizing a high speed enhancement/depletion mode inverter pair followed by a clocked signal isolation stage. ... | 12/12/1978 |
| 4117514 | Solid state imaging device A solid state imaging device capable of converting one-dimensional or two-dimensional optical information into an electrical signal is disclosed. A signal charge stored in each of a plurality of photo-electric converter elements, which is proportional to ... | 09/26/1978 |
| 4117546 | Interlaced CCD memory Disclosed is an interlaced serial-parallel-serial (SPS) charge coupled device (CCD) memory with improved clocking. By performing the interlacing as well as the serial-parallel-serial function with only seven clock pulses, less metallurgy and consequently ... | 09/26/1978 |
| 4110842 | Random access memory with memory status for improved access and cycle times A static random access memory which generates a memory status signal for improved performance. The same signal in a random access memory which enables data to go to the output is taken to form the leading edge of a memory status signal, indicating that ou... | 08/29/1978 |
| 4099069 | Circuit producing a common clear signal for erasing selected arrays in a MNOS memory system An MNOS memory array including circuitry to permit all of the memory devices comprising the array to be addressed for purposes of clearing the array by a block select and a clear signal as disclosed. The circuitry is arranged such that a plurality of arra... | 07/04/1978 |
| 4090096 | Timing signal generator circuit A timing signal generator includes a field-effect transistor having a drain supplied with a command signal and a source connected to an output node. The gate of the transistor is connected to a circuit node which is precharged to a voltage to render the t... | 05/16/1978 |
| 4087704 | Sequential timing circuitry for a semiconductor memory A semiconductor memory employs a variety of circuit elements which are used to manipulate the digital information stored within the rows and columns of the memory array. The circuit elements must be manipulated in an ordered sequence with proper relative ... | 05/02/1978 |
| 4072932 | Clock generator for semiconductor memory Disclosed is a read clock generator for use in a semiconductor memory. The read clock generator is comprised of a bistable amplifier and a differential voltage sensor. The bistable amplifier is activated during a read cycle; and it simulates the transient... | 02/07/1978 |
| 4070656 | Read/write speed up circuit for integrated data memories An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (fi... | 01/24/1978 |
| 4070657 | Current mode simultaneous dual-read/single-write memory device A current mode 20-bit memory is organized as four words each containing five bits. The memory comprises a clock circuit a data-in circuit, comprising a plurality of data selectors and master latch registers, a data-out circuit comprising two independent s... | 01/24/1978 |
| 4060794 | Apparatus and method for generating timing signals for latched type memories Apparatus and a method for generating timing signals to be utilized in latched type memories only when the address signals are valid. A CAS signal is generated in response to an RAS signal via a device which tracks the worst case delay of memory address s... | 11/29/1977 |
| 4044330 | Power strobing to achieve a tri state Apparatus and a method for coupling and uncoupling data-read lines of a memory array to a data bus. The data read-out lines of a memory array which is comprised of any combination of latched or non-latched tri-state memories are coupled to the data bus ut... | 08/23/1977 |
| 3997877 | Timing control means for a magnetic domain memory A non-volatile digital memory is utilized to generate digital pulses for controlling memory operations of a magnetic domain memory system. Each word stored in the memory contains data corresponding to the desired control signals. The digital memory synchr... | 12/14/1976 |
| 3993982 | Sequence control unit for a television time base corrector A sequence control unit for a digital video time base corrector used to process television signals to remove time base errors introduced during signal recording, reproducing, or transmission. In the time base corrector, incoming video signals are converte... | 11/23/1976 |
| 3978459 | High density MOS memory array A high density MOS integrated circuit memory array utilizing single device dynamic cells and a uniquely controlled sense amplifier. The loads of the sense amplifier are also used to precharge bit lines thereby reducing the number of devices used in prior ... | 08/31/1976 |
| 3976892 | Pre-conditioning circuits for MOS integrated circuits An integrated circuit includes circuitry thereon which includes a sensor circuit which detects a change in one of the plurality of inputs to the integrated circuit and generates one or more pre-conditioning signals which control circuitry to set up voltag... | 08/24/1976 |
| 3969706 | Dynamic random access memory misfet integrated circuit A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multipl... | 07/13/1976 |
| 3964030 | Semiconductor memory array A 1,024 bit semiconductor memory system, fabricated on a single integrated circuit chip, utilizes dynamic memory cells and low power dynamic control circuitry. An initial input control signal activates the control circuitry which internally generates all ... | 06/15/1976 |
| 3962686 | Memory circuit A memory circuit employing insulated-gate field-effect transistors includes a first circuit for generating a signal upon the completion of one of the circuit functions involved in the operation of the memory circuit. That signal is applied to a second cir... | 06/08/1976 |
| 3962689 | Memory control circuitry A control circuit for reading from, and writing into, a random access memory into which successive data entries are stored at addresses in sequential binary order. A scan generator provides a repeated sequence of all sequential binary order addresses to t... | 06/08/1976 |
| 3961315 | Information recording system An information recording system is disclosed in which a digital information recorded on a recording medium is read out, and the digital information is converted into optical patterns with darker and light densities so as to represent the logic "1" and "0.... | 06/01/1976 |
| 3959784 | High speed optical read-out of data stored in an array Data is stored in frames of fixed format at successive intervals along a ribbon or photographic film. Synchronizing marks on the storage medium indicate the location of each data frame and detection of each successive synchronizing mark triggers a light s... | 05/25/1976 |
| 3959781 | Semiconductor random access memory A random access memory system employing dynamic storage wherein each cell comprises a single active element. The memory employs MOS technology and is disposed on a silicon substrate. A plurality of sense amplifiers are disposed in a column substantially b... | 05/25/1976 |
| 3949384 | Synchronous shift register with series and parallel data input and basic position input A synchronous shift register has serial and parallel data inputs and a basic position input. The individual stages of the shift register are each constructed with a master-slave flip-flop which is fed back by way of a majority decision element. To the set... | 04/06/1976 |
| 3947829 | Logical circuit apparatus A plurality of logical control circuits each having a storage or delay function are driven by a writing-in clock pulse $c;1 and a reading-out clock pulse $c;2 supplied in common thereto and receiving output signals from a Read Only Memory constructe... | 03/30/1976 |
| 3943496 | Memory clocking system A solid state memory employs a plurality of memory cells each capable of storing either of two different binary values. The memory cells require periodic application of a refresh pulse to the memory cell to, without rewriting, enhance at least one of the ... | 03/09/1976 |
| 3941686 | Inspection machine memory An improved memory for a glass container inspection machine. In one common form of glass container inspection machines, the containers are indexed through multiple stations where they are inspected for various attributes. Rejection of defective containers... | 03/02/1976 |
| 3940720 | Recirculating electric and acoustic tapped delay line The recirculating tapped delay line in accordance with the invention is a combination electrical and acoustic recirculation network that includes a selected number of acoustic surface wave circulating subloops included in an electrical primary feedback lo... | 02/24/1976 |
| 3935565 | Signal generator comprising an addressable memory A circuit for and a method of utilizing an addressable memory as the generator of timing pulse signals is disclosed. The memory has n separate input terminals for receiving the n-bits of an n-bit address word to address one of the 2n addressabl... | 01/27/1976 |
