Bizarre Patents
Hands free towel carrying system
A hands free towel carrying system for coupling a towel to a user to prevent loss, theft or contamination.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7286383 | Bit line sharing and word line load reduction for low AC power SRAM architecture In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduc... | 10/23/2007 |
| 7287119 | Integrated circuit memory device with delayed write command processing An integrated circuit memory device having delayed write command processing includes a first set of pins coupled to a memory core, the first set of pins to receive a row address followed by a column address. A second set of pins, coupled to memory core, are used to ... | 10/23/2007 |
| 7286432 | Temperature update masking to ensure correct measurement of temperature when references become unstable Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature... | 10/23/2007 |
| 7287143 | Synchronous memory device having advanced data align circuit A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in resp... | 10/23/2007 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7286397 | Clock synchronized nonvolatile memory device A nonvolatile memory apparatus including a control circuit, plural terminals having clock, command and other terminals, data and command registers, and plural nonvolatile memory cells. The clock terminal receives a clock signal and the command terminal receives comm... | 10/23/2007 |
| 7282974 | Delay locked loop A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a ... | 10/16/2007 |
| 7282977 | Duty cycle correction device Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first si... | 10/16/2007 |
| 7283404 | Content addressable memory including a dual mode cycle boundary latch A content addressable memory (CAM) system is disclosed including a dual mode cycle boundary latch (CBL). The CBL includes a master latch coupled to a slave latch. The CBL operates in a high speed functional mode and a lower speed test mode. In the high speed functio... | 10/16/2007 |
| 7283418 | Memory device and method having multiple address, data and command buses A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by ... | 10/16/2007 |
| 7283421 | Semiconductor memory device The present invention provides a semiconductor memory device for reducing a power consumption. A semiconductor memory device includes a command decoding unit for decoding a plurality of commands; a driving signal generation unit for generating a plurality of driving... | 10/16/2007 |
| 7282972 | Bias generator with feedback control A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is v... | 10/16/2007 |
| 7284268 | System and method for a routing device to securely share network data with a host utilizing a hardware firewall A system and method for providing the ability to selectively share data in a network routing device with an associated host. The system and method employs a hardware firewall in the routing device which restricts the host such that it can only access areas in shared... | 10/16/2007 |
| 7282947 | Memory module and method having improved signal routing topology A registered memory module includes several memory devices coupled to a register through a plurality of transmission lines forming a symmetrical tree topology. The tree includes several branches each of which includes two transmission lines coupled only at its ends ... | 10/16/2007 |
| 7280431 | Method of generating an internal clock for a semiconductor memory device and semiconductor memory device using the same In a method of generating an internal clock for a semiconductor memory device, a doubled clock is generated during operation in a high-speed test mode in response to an external clock. A data clock is generated by delaying the doubled clock so that data read from a ... | 10/09/2007 |
| 7280410 | System and method for mode register control of data bus operating mode and impedance A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signa... | 10/09/2007 |
| 7280417 | System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the... | 10/09/2007 |
| 7280429 | Data latch circuit of semiconductor device and method for latching data signal A data latch circuit for latching a data and a method for latching a data signal in synchronization with a clock signal are provided. The data latch circuit includes: a data input controller for outputting a first data transition detection signal in response to a fi... | 10/09/2007 |
| 7280430 | Semiconductor memory device Disclosed herein is a semiconductor memory device for reducing an unnecessary current consumption occurred in an idle state or an active state. The semiconductor memory device includes a driving clock supply unit for supplying a driving clock during a read or a writ... | 10/09/2007 |
| 7280398 | System and memory for sequential multi-plane page memory operations A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for a... | 10/09/2007 |
| 7280406 | Semiconductor memory device Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition.... | 10/09/2007 |
| 7280419 | Latency counter having frequency detector and latency counting method thereof The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a f... | 10/09/2007 |
| 7280545 | Complex adaptive routing system and method for a nodal communication network A complex adaptive routing system and method for routing data packets in a nodal network, in particular, an ad-hoc nodal network. Each data packet contains data representing its routing strategy for routing to a destination node. When a node receives the data packet... | 10/09/2007 |
| 7281079 | Method and apparatus to counter mismatched burst lengths Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and c... | 10/09/2007 |
| 7279938 | Delay chain integrated circuits having binary-weighted delay chain units with built-in phase comparators therein Delay-locked loop integrated circuits include a delay chain having a plurality of delay chain units. The delay chain may be a binary-weighted delay chain and the delay chain units may be arranged in ascending or descending order (e.g., x1, x2, x4, x8, . . . ) accord... | 10/09/2007 |
| 7280054 | Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys in... | 10/09/2007 |
| 7279946 | Clock controller with integrated DLL and DCC A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node receiving a reference clock represented by a least one clock signal. Th... | 10/09/2007 |
| 7280336 | Transient voltage detecting circuit The invention provides a transient voltage detecting circuit for detecting a transient voltage occurring at a power supply or a ground of an electronic system. The circuit according to the invention includes a plurality of detecting units of which the outputs are in... | 10/09/2007 |
| 7281078 | Bank structure storage control device and paper matter authentication device A storage control device of bank structure is provided which comprises a CPU 1 and a storage 2 connected to CPU 1. Storage 2 detects and temporarily holds one of the bank addresses 0DF00h-7DF07h of the bank memories 9 to be read ou... | 10/09/2007 |
| 7280386 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/09/2007 |
| 7280555 | System and method employing algorithms and protocols for optimizing carrier sense multiple access (CSMA) protocols in wireless networks A system and method for achieving enhanced CSMA/CA which improves channel availability and quality of service (QoS) in a wireless communications network. The system and method establish channels to enable communication between nodes in a communication network, based... | 10/09/2007 |
| 7278060 | System and method for on-board diagnostics of memory modules A memory hub includes an on-board diagnostic engine through which diagnostic testing and evaluation of the memory system can be performed. The memory hub includes a link interface for receiving memory requests for access to memory devices of the memory system and a ... | 10/02/2007 |
| 7277357 | Method and apparatus for reducing oscillation in synchronous circuits Control signal oscillation filtering circuits, delay-locked loops, clock synchronization methods and devices and system incorporating control signal oscillation filtering circuits is described. An oscillation filtering circuit includes a first oscillation filter con... | 10/02/2007 |
| 7277988 | System, method and storage medium for providing data caching and data compression in a memory subsystem A cascaded interconnect system including a memory controller, one or more memory modules, an upstream memory bus and a downstream memory bus. The one or more memory modules include a first memory module with cache data. The memory modules and the memory controller a... | 10/02/2007 |
| 7277354 | Apparatus and method for updating data in a dual port memory A dual port memory is updated at substantially the same data sampling rate as a clock frequency of the dual port memory. The dual port memory stores data relating to each different parameter value in a stream of data samples, and provides the stored data from an add... | 10/02/2007 |
| 7277996 | Modified persistent auto precharge command protocol system and method for memory devices A method of operating a memory device includes placing the memory device in a persistent auto precharge mode of operation, applying a disable command to the memory device, and disabling the persistent auto precharge mode of operation in response to the applied disab... | 10/02/2007 |
| 7278033 | Method and a system for determining the power consumption in connection with an electronic device, and an electronic device The present invention relates to a method and a system for determining the power consumption in an electronic device, to which a peripheral device is connected, to which the power is supplied from the electronic device. At least a first maximum value and a second ma... | 10/02/2007 |
| 7277334 | Method and apparatus for synchronization of row and column access operations A circuit for synchronizing row and column access operations in a semiconductor memory having an array of bit line pairs, word lines, memory cells, sense amplifiers, and a sense amplifier power supply circuit for powering the sense amplifiers, the circuit comprising... | 10/02/2007 |
| 7277344 | Semiconductor storage device and operating method therefor A semiconductor storage device according to an embodiment of the present invention includes: a plurality of word lines; a plurality of memory cells corresponding to the plurality of word lines; and a refresh circuit for sequentially driving the plurality of word lin... | 10/02/2007 |
