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| Number | Title | Issue Date |
| 8107314 | Semiconductor storage device and method for producing semiconductor storage device A semiconductor storage device comprises a timing control circuit that generates a signal for controlling at least one of a read operation and a write operation; an input-signal pad; a plurality of control-signal pads; and a switch circuit coupled to at least one of... | 01/31/2012 |
| 8036062 | Semiconductor memory device and method for driving the same A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL c... | 10/11/2011 |
| 8031539 | Memory device and memory system comprising a memory device and a memory control device In an embodiment, a memory device comprises a clock generating unit being configured to generate a read clock signal, the clock generating unit being connected to a first clock signal contact configured to send the read clock signal, and the clock generating unit be... | 10/04/2011 |
| 7983110 | Circuit and method for controlling a clock synchronizing circuit for low power refresh operation A method and apparatus is provided for idling a clock synchronizing circuit during at least a portion of time during execution of a refresh operation in a memory device. In a memory device receiving an external clock signal, a method and apparatus for executing a re... | 07/19/2011 |
| 7936635 | Semiconductor memory device and method for driving the same A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL c... | 05/03/2011 |
| 7872940 | Semiconductor memory device and method for testing the same Semiconductor memory device and method for testing the same includes a unit for characterized in that a burst length is increased in a test of a read operation and a write operation and a unit for connecting a plurality of banks to one data pad by sequentially and o... | 01/18/2011 |
| 7864623 | Semiconductor device having latency counter A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and secon... | 01/04/2011 |
| 7796463 | Self-feedback control pipeline architecture for memory read path applications A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection a... | 09/14/2010 |
| 7715272 | Semiconductor device having latency counter A semiconductor device includes a latency setting circuit setting the latency, an input command circuit outputting a normal-phase (reverse-phase) command signal obtained by capturing an input command signal using a normal-phase (reverse-phase) clock, first and secon... | 05/11/2010 |
| 7710817 | Semiconductor memory device having a delay locked loop (DLL) and method for driving the same A semiconductor memory device includes: a modulation controller for generating a modulation control signal for controlling a frequency modulation operation; a delay locked loop (DLL) circuit for performing a delay locking operation to generate first and second DLL c... | 05/04/2010 |
| 7688671 | Semiconductor memory chip with on-die termination function A semiconductor memory chip with an On-Die Termination (ODT) function is disclosed, which comprises a delay locked loop (DLL) circuit, a synchronous circuit, an asynchronous circuit, a select signal generator, and a selector. The DLL circuit is configured to produce... | 03/30/2010 |
| 7679986 | Data latch controller of synchronous memory device Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write str... | 03/16/2010 |
| 7633831 | Semiconductor memory and operating method of same An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, u... | 12/15/2009 |
| 7630275 | Latency counter A latency counter includes: a point-shift type FIFO circuit having plural latch circuits connected in parallel, each latch circuit including an input gate and an output gate, and having an internal command MDRDT supplied in common to the input gates; and a selector ... | 12/08/2009 |
| 7609583 | Selective edge phase mixing Electronic apparatus, systems, and methods to implement selective edge phase mixing are disclosed. A selective edge phase mixing system includes a processor and memory device configured to perform operations in synchronization with transitions of an externally provi... | 10/27/2009 |
| 7577056 | System and method for using a DLL for signal timing control in a eDRAM The present invention discloses an embedded dynamic random access memory (eDRAM) comprising a clock signal, at least one delay-locked loop (DLL) circuit coupled to the clock signal and configured to generate a plurality of control signals each having a predetermined... | 08/18/2009 |
| 7567483 | Semiconductor memory device and method for operating the same A semiconductor memory device includes a first clock input unit for generating a first clock signal based on a signal at an intersection of a system clock signal and an inverted system clock signal; a second input unit for generating a second clock signal based on a... | 07/28/2009 |
| 7564737 | Memory data transfer In one aspect, there is provided a method for controlling data output by a memory device. The method may include receiving a first clock signal having a first frequency. Moreover, a second and third clock signals may be produced from the first clock signal. The seco... | 07/21/2009 |
| 7558150 | Memory controller with staggered request signal output A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relati... | 07/07/2009 |
| 7558149 | Method and apparatus to control sensing time for nonvolatile memory One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In ano... | 07/07/2009 |
| 7499370 | Synchronous semiconductor memory device A synchronous semiconductor memory device includes an output control signal generator, which generates an output control signal corresponding to a signal obtained by delaying a read information signal in response to a delay internal clock signal obtained by dividing... | 03/03/2009 |
| 7492663 | Storage device with protection against inadvertent writing The present invention provides a storage device. The storage device includes a reset signal terminal, a clock signal terminal, a non-volatile memory, and a pull down resistance. The reset signal terminal is electrically connected to external equipment at a contact p... | 02/17/2009 |
| 7489586 | Semiconductor memory device and driving method thereof A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a... | 02/10/2009 |
| 7480203 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM A method of synchronizing counters in two different clock domains within a memory device is comprised of generating a start signal for initiating production of a running count of clock pulses of a read clock signal in a first counter downstream of a locked loop and ... | 01/20/2009 |
| 7477568 | Using common mode differential data signals of DDR2 SDRAM for control signal transmission A double-data-rate two synchronous dynamic random access (DDR2 ) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory ... | 01/13/2009 |
| 7466622 | Method for controlling time point for data output in synchronous memory device Disclosed is a method for controlling a time point for data output in a synchronous memory device, which varies a time point of an internal read command of the synchronous memory device, which is generated in response to an external read command according to the CAS... | 12/16/2008 |
| 7457192 | Semiconductor memory device and module for high frequency operation The present invention relates to a synchronous semiconductor memory device with double data rate, and more particularly, to a synchronous semiconductor memory device for inputting and outputting data using a free-running clock and inserting a preamble indicative of ... | 11/25/2008 |
| 7457191 | Apparatus and method of generating output enable signal for semiconductor memory apparatus A timing signal generator generates a timing signal when an external clock is synchronized with a predetermined internal timing. A frequency-divided clock generator divide a frequency of a DLL (Delay Locked Loop).clock so as to generate an even-numbered divided cloc... | 11/25/2008 |
| 7457190 | Data latch controller of synchronous memory device Disclosed is a data input circuit of a synchronous memory device for detecting and amplifying data, and transferring the amplified data for storage, which including: a write strobe signal converter for receiving a write strobe signal, dividing the received write str... | 11/25/2008 |
| 7443761 | Loop filtering for fast PLL locking Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes... | 10/28/2008 |
| 7440304 | Multiple string searching using ternary content addressable memory A method and apparatus for multiple string searching using a ternary content addressable memory. The method includes receiving a text string having a plurality of characters and performing an unanchored search of a database of a stored patterns matching one or more ... | 10/21/2008 |
| 7441138 | Systems and methods capable of controlling multiple data access using built-in-timing generators When receiving request commands from different hosts, a data system generates corresponding phase control signals and access signals based on the formats of each request command. Based on the phase control signals, timing signals corresponding to respect request com... | 10/21/2008 |
| 7430147 | Precharge apparatus A precharge circuit prevents voltage dropping of a local input/output line in a semiconductor memory apparatus. The precharge circuit includes at least one pair of pull-up and pull-down precharge circuits. When a local input/output line precharge signal is enabled, ... | 09/30/2008 |
| 7430143 | Delay locked operation in semiconductor memory device A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clo... | 09/30/2008 |
| 7428182 | Electronic circuit system, and signal transmission method, to improve signal transmission efficiency and simplify signal transmission management An electronic circuit system has at least three macro circuits and a plurality of signal lines for connecting the macro circuits to one another into a loop. Each of the macro circuits includes a logic circuit and a memory circuit and has a plurality of input termina... | 09/23/2008 |
| 7426144 | Semiconductor storage device A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in sync... | 09/16/2008 |
| 7426145 | Synchronous semiconductor memory device having on-die termination circuit and on-die termination method A synchronous semiconductor memory device having an on-die termination (ODT) circuit, and an ODT method, satisfy ODT DC and AC parameter specifications and perform an adaptive impedance matching through an external or internal control, by executing an ODT operation ... | 09/16/2008 |
| 7423927 | Wave pipelined output circuit of synchronous memory device Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low freque... | 09/09/2008 |
| 7420864 | Temperature update masking to ensure correct measurement of temperature when references become unstable Embodiments of the invention generally provide methods and apparatuses for updating a temperature measurement. In one embodiment, the temperature measurement is performed by a temperature sensor using one or more reference signals. A signal to update the temperature... | 09/02/2008 |
| 7421548 | Memory system and method for two step memory write operations A method and apparatus for storing data in a memory device is described. The apparatus is configured to perform the following steps. The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation... | 09/02/2008 |
