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| Number | Title | Issue Date |
| 8169852 | Memory control circuit, control method, and storage medium A circuit configured to change a mode of a plurality of memory devices having a power saving mode includes a command queue configured to hold memory access, and a cancellation unit configured to cancel the power saving mode of target devices of the memory access hel... | 05/01/2012 |
| 8144542 | Semiconductor memory apparatus and method for operating the same A semiconductor memory apparatus includes a clock input unit configured to receive a system clock and a data clock, a data clock phase regulation unit configured to regulate a frequency of the data clock, and delay the data clock by a delay varied in accordance with... | 03/27/2012 |
| 8130570 | Data transfer circuit A data transfer circuit includes: an asynchronous memory to which transfer data is written from a first clock domain with a first clock and from which the written transfer data is read to a second clock domain with a second clock; a scan flip-flop whose input termin... | 03/06/2012 |
| 8102730 | Single-clock, strobeless signaling system A signaling system includes a signaling path, a master device coupled to the signaling path, a slave device coupled to the signaling path, and a clock generator. The slave device includes timing circuitry to generate an internal clock signal having a phase offset re... | 01/24/2012 |
| 7911874 | Semiconductor integrated circuit An interface conversion macro converts a signal compliant with a system interface specification output from a controller to a signal compliant with a memory interface specification, and outputs the same to a memory interface part, and it also converts a signal outpu... | 03/22/2011 |
| 7778107 | Decoding control with address transition detection in page erase function Circuits and methods are provided for controlling multi-page erase operations in flash memory. The page address of each address of a multi-page erase operation is latched in wordline decoders. A page select reset generator circuit processes the block addresses of ea... | 08/17/2010 |
| 7751276 | Semiconductor memory device capable of performing page mode operation A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a seco... | 07/06/2010 |
| 7697371 | Circuit and method for calibrating data control signal A circuit for calibrating a data control signal includes a time-delay compensation circuit and a voltage-control delay circuit. The time-delay compensation circuit receives two complementary signals and a direct current voltage which has two voltage cross points wit... | 04/13/2010 |
| 7656745 | Circuit, system and method for controlling read latency A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase o... | 02/02/2010 |
| 7626885 | Column path circuit A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates ... | 12/01/2009 |
| 7599246 | Delay locked loop implementation in a synchronous dynamic random access memory A clock applying circuit for a synchronous memory is comprised or a clock input for receiving a clock input signal, apparatus connected to the synchronous memory for receiving a driving clock signal, and a tapped delay line for receiving the clock input signal and f... | 10/06/2009 |
| 7596053 | Integrated memory controller A circuit for reading data from a buffer memory, which is Synchronous Dynamic Random access Memory (“SDRAM”), or Double Data Rate-Synchronous Dynamic Random Access Memory (“DDR”) comprises logic for managing programmable clock signal relationships such that ... | 09/29/2009 |
| 7593276 | Semiconductor memory device A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy... | 09/22/2009 |
| 7489589 | MRAM internal clock pulse generation with an ATD circuit and the method thereof A magnetic random access memory having an extended address transition detection circuit having a chip enable input, a chip write enable input, a data bus connection, and an address bus connection. The extended address transition detection circuit has an extended tra... | 02/10/2009 |
| 7477569 | Semiconductor memory device capable of performing page mode operation A semiconductor memory device adapted to perform a page mode operation comprises a first address transition detector adapted generate a first clock signal upon detecting a transition of a start address, a second address transition detector adapted to generate a seco... | 01/13/2009 |
| 7450466 | Data input device of semiconductor memory device A data input device of a semiconductor memory device can reduce unnecessary current consumption occurring according to a setting of a bandwidth. The data input device includes: a bandwidth signal input part for receiving a bandwidth signal for setting a data bandwid... | 11/11/2008 |
| 7443743 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 10/28/2008 |
| 7443752 | Semiconductor memory device amplifying data A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first... | 10/28/2008 |
| 7430141 | Method and apparatus for memory data deskewing A memory interface (20) for receiving memory signals individually synchronizes data signals to a delayed strobe signal in order to reduce the spread of the data signals prior to sampling. A delay is increased for an individual data signal if it transitions pr... | 09/30/2008 |
| 7428186 | Column path circuit A column path circuit includes address transition detectors which detect level transition of page address signals, thereby outputting transition detection signals each having a predetermined enable period, respectively. A detection signal coupler logically operates ... | 09/23/2008 |
| 7426153 | Clock-independent mode register setting methods and apparatuses Mode register setting methods and apparatuses for semiconductor devices are provided in order to suppress a limit in the frequency at which a mode register of a semiconductor device operates from occurring before the semiconductor device carries out a typical write ... | 09/16/2008 |
| 7423919 | Method and system for improved efficiency of synchronous mirror delays and delay locked loops A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multipl... | 09/09/2008 |
| 7408814 | Method and apparatus for filtering output data Apparatus and methods for filtering spurious output transitions with an adaptive filtering circuit which tracks the memory architecture and form factors with a reduced speed penalty. The filtering is selectable by a fuse option. ... | 08/05/2008 |
| 7376044 | Burst read circuit in semiconductor memory device and burst data read method thereof A semiconductor memory device conducts a burst read operation that avoids interrupt loading on a system. The memory device includes a memory cell array, a sense amplifier, a latch circuit and a burst mode control unit. The sense amplifier is configured to sequential... | 05/20/2008 |
| 7372723 | State save-on-power-down using GMR non-volatile elements The semiconductor industry seeks to reduce the risk of traditional volatile storage devices with improved non-volatile storage devices. The increased demand for a significantly advanced, efficient, and non-volatile data retention technique has driven the development... | 05/13/2008 |
| 7372768 | Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of... | 05/13/2008 |
| 7372754 | Method and apparatus for controlling slope of word line voltage in nonvolatile memory device A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The devi... | 05/13/2008 |
| 7369457 | Semiconductor memory device A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense ... | 05/06/2008 |
| 7362619 | Data strobe synchronization circuit and method for double data rate, multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates... | 04/22/2008 |
| 7358785 | Apparatus and method for extracting a maximum pulse width of a pulse width limiter An apparatus and method for extracting a maximum pulse width of a pulse width limiter are provided. The apparatus and method of the illustrative embodiments performs such extraction using a circuit that is configured to eliminate the majority of the delay cells util... | 04/15/2008 |
| 7359278 | Method for producing an integrated memory module A method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out operations in accordance with a predetermined specification of the memo... | 04/15/2008 |
| 7355920 | Write latency tracking using a delay lock loop in a synchronous DRAM A method and circuitry for improved write latency tracking in a SDRAM is disclosed. In one embodiment, a delay locked loop is used in the command portion of the write path, and receives the system clock as its reference input. The DLL includes a modeled delay which ... | 04/08/2008 |
| 7355902 | Methods and apparatus for inline characterization of high speed operating margins of a storage element A method for inline characterization of at least one high speed operating margin of a storage element is provided. An output of at least one latch of the integrated circuit device is transitioned from a first output logic state to a second output logic state. The st... | 04/08/2008 |
| 7349270 | Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low... | 03/25/2008 |
| 7349269 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 03/25/2008 |
| 7342838 | Programmable logic device with a double data rate SDRAM interface Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with th... | 03/11/2008 |
| 7339839 | Triggering of IO equilibrating ending signal with firing of column access signal A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of th... | 03/04/2008 |
| 7336559 | Delay-locked loop, integrated circuit having the same, and method of driving the same A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase ... | 02/26/2008 |
| 7333377 | Test mode control device using nonvolatile ferroelectric memory A test mode control device using a nonvolatile ferroelectric memory enables a precise test of characteristics of a memory cell array by changing a reference voltage and timing regulated for a memory cell test in a software system without extra processes. In an embod... | 02/19/2008 |
| 7330382 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 02/12/2008 |
