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| Number | Title | Issue Date |
| 7554878 | Synchronous memory device A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respe... | 06/30/2009 |
| 7443707 | Magnetic random access memory array with free layer locking mechanism and method of its use A method of using an MTJ MRAM cell element having two magnetization states of greater and lesser stability. During switching, the free layer is first placed in the less stable state by a word line current, so that a small bit line current can switch its magnetizatio... | 10/28/2008 |
| 7405958 | Magnetic memory device having XP cell and Str cell in one chip According to the semiconductor memory device of this invention, an XP type MRAM cell array and an STr type MRAM cell array are formed on a single chip. The XP type MRAM cell array is laid over the STr type MRAM cell array to form a layered structure. The STr type MR... | 07/29/2008 |
| 7372732 | Pulse width converged method to control voltage threshold (Vt) distribution of a memory cell A method of operating on a plurality of non-volatile multi-level memory cells is disclosed. The memory cells have at least a first, second, third and fourth program level. Each of program levels corresponds to a different binary state and has a voltage threshold dis... | 05/13/2008 |
| 7372762 | Semiconductor memory device The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage generator for use in the semiconductor memory device includes a cell plate voltage generator, a driving v... | 05/13/2008 |
| 7370138 | Mobile communication terminal including NAND flash memory and method for booting the same A mobile communication terminal with a NAND flash memory is described. The terminal includes a memory for storing address information indicative of a start address of a specific area including boot data to be read from the NAND flash memory; and a sub-controller for... | 05/06/2008 |
| 7369438 | Combo memory design and technology for multiple-function java card, sim-card, bio-passport and bio-id card applications A combination volatile and nonvolatile memory integrated circuit has at least one volatile memory array placed on the substrate and multiple nonvolatile memory arrays. The volatile and nonvolatile memory arrays have address space associated with each other such that... | 05/06/2008 |
| 7369456 | DRAM memory with autoprecharge A DRAM memory comprises a memory cell bank comprised of memory cells being activated by means of internal row and column access instructions, a command decoder generating, dependent on an external memory access instruction, at least one column access instruction wit... | 05/06/2008 |
| 7365389 | Memory cell having enhanced high-K dielectric A semiconductor memory device may include an intergate dielectric layer of a high-K, high barrier height dielectric material interposed between a charge storage layer and a control gate. With this intergate high-K, high barrier height dielectric in place, the memory... | 04/29/2008 |
| 7366992 | Method and system for displaying and/or manipulating medical image data In one embodiment, a medical image viewer in compliance with a medical image standard is provided, and a file in compliance with the medical image standard is provided to the medical image viewer. The medical image standard specifies a first field for data not in co... | 04/29/2008 |
| 7364090 | Memory cards having two standard sets of contacts Enclosed re-programmable non-volatile memory cards include at least two sets of electrical contacts to which the internal memory is connected. The two sets of contacts have different patterns, preferably in accordance with two different contact standards such as a m... | 04/29/2008 |
| 7358520 | Semiconductor memory cell, method for fabricating it and semiconductor memory device A semiconductor memory cell, a method for fabricating it and a semiconductor memory device. A phase change material region of a storage element of the semiconductor memory cell has been or is formed as a lining region of a wall region of a contact recess which passe... | 04/15/2008 |
| 7355873 | Highly integrated ternary semiconductor memory device A TCAM (ternary content addressable memory) cell array is provided with a search input node into which one bit of search data is inputted, a plurality of data input nodes into which a bit corresponding to one bit of search data is inputted, and a plurality of memory... | 04/08/2008 |
| 7352603 | Apparatus and methods for optically-coupled memory systems Optically-coupled memory systems are disclosed. In one embodiment, a system memory includes a carrier substrate, and a controller attached to the carrier substrate and operable to transmit and receive optical signals, and first and second memory modules. The module ... | 04/01/2008 |
| 7348268 | Controlled breakdown phase change memory device A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the m... | 03/25/2008 |
| 7342832 | Bit line pre-settlement circuit and method for flash memory sensing scheme A flash memory array includes a reference bit line on which a reference current is imposed. During read operation, bit lines selected for reading are connected to current-to-voltage converters, each of which generates an output voltage based upon the input current f... | 03/11/2008 |
| 7339849 | Internal voltage supply circuit of a semiconductor memory device with a refresh mode An internal voltage supply circuit may Include a first internal voltage generator for receiving an external voltage and generating a first internal voltage, a second internal voltage generator for generating a second internal voltage lower than the first internal vo... | 03/04/2008 |
| 7340356 | Method and system for reading the resistance state of junctions in crossbar memory Various embodiments of the present invention are directed to methods for determining the resistance state of nanowire-crossbar junctions, and can also be used to determine the resistance state of sub-microscale crossbar junctions. A pair of wires interconnected thro... | 03/04/2008 |
| 7339823 | Nonvolatile semiconductor storage apparatus and method of driving the same A memory cell array is logically divided into a plurality of regions having different reading speeds, the respective regions having the different reading speeds include region information storage regions for storing region information in which at least two addresses... | 03/04/2008 |
| 7336556 | Magnetic non-volatile memory device A non-volatile magnetic memory device is proposed, which provides sufficient magnetic shielding performance for external magnetic fields. A first magnetic shield layer 60a and a second magnetic shield layer 60b, both made of a soft magnet... | 02/26/2008 |
| 7335992 | Semiconductor apparatus with improved yield The semiconductor apparatus includes a pad; a first line layer placed immediately beneath the pad; and a lattice-shaped contact being between the pad and the first line layer. ... | 02/26/2008 |
| 7336098 | High speed memory modules utilizing on-pin capacitors Apparatus and method for producing memory modules having a plurality of branches connected to a memory bus, each branch containing at least one dynamic random access memory (DRAM) device or SDRAM device connected to the memory bus via at least one transmission signa... | 02/26/2008 |
| 7333371 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device including a memory cell array with electrically rewritable and non-volatile memory cells arranged therein, and a sense amplifier circuit for reading said memory cell array, wherein the sense amplifier circuit includes: a fi... | 02/19/2008 |
| 7330720 | Time zone based phone services A method and apparatus provides for, as a part of call setup and routing whenever a calling party calls a called party, which includes determining a local time for the called party prior to completing call setup. If the local time is within a specified time range, a... | 02/12/2008 |
| 7323734 | Phase changeable memory cells A phase changeable memory cell is disclosed. According to embodiments of the invention, a phase changeable memory cell is formed that has a reduced contact area with one of the electrodes, compared to previously known phase changeable memory cells. This contact area... | 01/29/2008 |
| 7323903 | Soft core control of dedicated memory interface hardware in a programmable logic device The present invention is directed to a soft core logic circuit implemented in a PLD that estimates an appropriate phase delay and applies the phase shift to a read strobe signal to align its rising and falling edges at the center of a data sampling window associated... | 01/29/2008 |
| 7319635 | Memory system with registered memory module and control method A memory module and related method are disclosed. The memory module comprises a clock generator configured to generate first and second internal clock signals in relation to an external clock signal, and a register configured to receive the first and second internal... | 01/15/2008 |
| 7319608 | Non-volatile content addressable memory using phase-change-material memory elements A non-volatile content addressable memory cell comprises: a first phase change material element, the first phase change material element having one end connected to a match-line; a first transistor, the first transistor having a gate connected to a word-line, a sour... | 01/15/2008 |
| 7317250 | High density memory card assembly A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare sem... | 01/08/2008 |
| 7317636 | Nonvolatile semiconductor memory, a data write-in method for the nonvolatile semiconductor memory and a memory card A nonvolatile semiconductor memory includes a memory cell array, a page buffer that is connected to the memory cell array and retains program verification results of a write-in operation of repeating data write-in and program verification, a bit scan circuit that is... | 01/08/2008 |
| 7315056 | Semiconductor memory array of floating gate memory cells with program/erase and select gates A memory device, and method of making and operating the same, including a substrate of semiconductor material of a first conductivity type, first and second spaced apart regions in the substrate of a second conductivity type with a channel region therebetween, an el... | 01/01/2008 |
| 7301802 | Circuit arrays having cells with combinations of transistors and nanotube switching elements Circuit arrays having cells with combinations of transistors and nanotube switches. Under one embodiment, a circuit array includes a plurality of cells arranged in an organization of words, each word having a plurality of bits. Each cell is responsive to a bit line,... | 11/27/2007 |
| 7294547 | SONOS memory cell having a graded high-K dielectric A semiconductor memory device may include an intergate dielectric layer of high-K dielectric materials interposed between a charge storing layer and a control gate. The high-K materials may be deposited in such a manner that the materials are gradually graded with r... | 11/13/2007 |
| 7283395 | Memory device and method for operating the memory device A memory device comprises a memory cell array (1) with a multitude of memory cells (111). Each of the memory cells (111) is assigned to one of a multitude of blocks (15). Each memory cell (111) is accessible by an access signal in ... | 10/16/2007 |
| 7280394 | Field effect devices having a drain controlled via a nanotube switching element Field effect devices having a drain controlled via a nanotube switching element. Under one embodiment, a field effect device includes a source region and a drain region of a first semiconductor type and a channel region disposed therebetween of a second semiconducto... | 10/09/2007 |
| 7280054 | Integrated circuit interface that encodes information using at least one input signal sampled at two consecutive edge transitions of a clock signal An integrated circuit, such as a dynamic RAM, includes a plurality of terminals for coupling to signal lines. One of the signal lines is an input signal line that conveys a clock signal, and at least one other signal line is also an input signal line that conveys in... | 10/09/2007 |
| 7266035 | Self-aligned row-by-row dynamic VDD SRAM A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is conne... | 09/04/2007 |
| 7263581 | System and method for accessing and verifying the validity of data content stored in the cache memory on disk A system and a method for accessing and verifying the validity of data content stored in the cache memory on disk are proposed, which is applied in a data accessing system through the use of a master disk controller or a slave disk controller. For data accessing pur... | 08/28/2007 |
| 7263044 | Information storage medium and method and apparatus for recording/reproducing data on/from the same An information storage medium and a method and apparatus for recording/reproducing data on/from the information storage medium. The information storage medium includes a plurality of recording layers, each having a user data area, on which data can be recorded by a ... | 08/28/2007 |
| 7262999 | System and method for preventing read margin degradation for a memory array An ultra cycling nitride read only memory (NROM) device is coupled to a NROM array such that both bits of the ultra cycling NROM device will be erased when all NROM devices of the NROM array are erased. The ultra cycling NROM device is then programmed at its right b... | 08/28/2007 |
