Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 8164972 | Address decoder An address decoder that includes a plurality of predecoders configured to (i) receive and logically combine a clock signal and address signals and (ii) generate addresses and complementary addresses. At least one of the plurality of precoders includes a first logic ... | 04/24/2012 |
| 8154948 | Method of operating nonvolatile memory device A method of operating a nonvolatile memory device includes supplying a variable voltage of a first voltage level to a selected page buffer and supplying the variable voltage to a first bit line, coupled to a selected memory cell selected for data reading, for a firs... | 04/10/2012 |
| 8139438 | Semiconductor storage device and memory system A semiconductor storage device includes an external terminal to which a first signal is supplied, a core circuit, and an access operation control circuit that generates a signal indicating an access operation mode to the core circuit for subsequent cycles based on a... | 03/20/2012 |
| 8134885 | High-speed compression architecture for memory Memory design techniques are disclosed that provide a high compression ratio at no loss in speed. The techniques can be embodied, for instance, in heterojunction bipolar transistor (HBT) based ROMs. By embedding compression logic (e.g., XOR) functionality directly i... | 03/13/2012 |
| 8077538 | Address decoder and/or access line driver and method for memory devices Address decoders and access line drivers are provided. One such row decoder and access line driver receives power supply voltages in a manner that prevents CHC damage and avoids GIDL currents in transistors in the decoder and driver. The row decoder and a latch in t... | 12/13/2011 |
| 8068383 | Semiconductor integrated circuit having address control circuit A semiconductor IC in which a least significant bit of an external address signal is fixed to a signal level, the semiconductor integrated circuit includes an address control circuit configured to produce a carry signal, when a test mode signal is activated, in resp... | 11/29/2011 |
| 8050135 | Semiconductor memory device A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and dis... | 11/01/2011 |
| 8023357 | Address converting circuit and semiconductor memory device using the same A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal an... | 09/20/2011 |
| 8004929 | Semiconductor memory device and control method thereof A semiconductor memory device includes: a command latch circuit that latches a command signal; an address latch circuit that latches an address signal; a mode latch circuit that latches a mode signal; and a command decoder that selects the address latch circuit in r... | 08/23/2011 |
| 8000165 | Self reset clock buffer in memory devices A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least on... | 08/16/2011 |
| 7990800 | Circuit and method for controlling DRAM column-command address The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an ... | 08/02/2011 |
| 7969813 | Write command and write data timing circuit and methods for timing the same Circuits, memories, and methods for latching a write command and later provided write data including write command and write data timing circuits. One such timing circuit includes internal write command latch to latch an internal write command in response to write c... | 06/28/2011 |
| 7948824 | Self reset clock buffer in memory devices A memory device includes a clock buffer circuit. The clock buffer circuit includes a cross-coupled logic circuit. The cross-coupled logic circuit has at least two logic gates in which an output of at least one of the logic gates is coupled to an input of at least on... | 05/24/2011 |
| 7933162 | Row addressing Embodiments are provided that include a row decoder, including a row activation path, having a row address converter with an output coupled to an input of a section replacement detector. Further embodiments provide a method including mapping an external row address ... | 04/26/2011 |
| 7911872 | Column/row redundancy architecture using latches programmed from a look up table A scheme for defective memory column or row substitution is disclosed which uses a programmable look-up table to store new addresses for column selection when certain column or row addresses are received. The new addresses are loaded into a programmable fuse latch e... | 03/22/2011 |
| 7898899 | Semiconductor integrated circuit and system The semiconductor integrated circuit comprises: a first buffer circuit that outputs a first output signal to an output terminal on receipt of a first input signal; a second buffer circuit that includes a circuit having a similar configuration to the first buffer cir... | 03/01/2011 |
| 7889592 | Non-volatile memory device and a method of programming the same Provided are a non-volatile memory device and a method of programming the same. The method includes: performing a program operation; performing a program verify read operation; and performing a pass/fail determine operation simultaneously with one of a verify recove... | 02/15/2011 |
| 7872939 | Semiconductor memory device A semiconductor memory device includes: a first address buffer configured to be used in a test mode and a normal mode and to receive more addresses in the test mode than in the normal mode; and a second address buffer configured to be used in the normal mode and dis... | 01/18/2011 |
| 7864622 | Low power multi-chip semiconductor memory device and chip enable method thereof A multi-chip semiconductor device capable of selectively activating and deactivating the individual semiconductor chips of the device and a chip enable method thereof are included. The individual semiconductor chips of the device are activated and deactivated in acc... | 01/04/2011 |
| 7848177 | Semiconductor integrated circuit device The semiconductor integrated circuit device includes: a first latch which can hold an output signal of the X decoder and transfer the signal to the word driver in a post stage subsequent to the X decoder; a second latch which can hold an output signal of the Y decod... | 12/07/2010 |
| 7843761 | Semiconductor memory device A semiconductor memory device is capable of securing margins of setup/hold times for receiving addresses. The device includes an address buffering unit, a data input/output line, a selecting unit and an output circuit. The address buffering unit buffers input addres... | 11/30/2010 |
| 7830742 | Semiconductor memory device and memory cell accessing method thereof A memory cell accessing method may include receiving an input address, determining whether the input address has been accessed at least a predetermined number of times, and converting a memory cell enabled by the input address when it is determined that the input ad... | 11/09/2010 |
| 7796461 | Semiconductor device having a plurality of memory chips A semiconductor device comprises a plurality of memory chips; and a controller configured to supply the plurality of memory chips with signals for controlling the plurality of memory chips. The plurality of memory chips include a chip selection signal input section ... | 09/14/2010 |
| 7796462 | Data flow control in multiple independent port A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a dev... | 09/14/2010 |
| 7782706 | Semiconductor memory device having a word line activation circuit and/or a bit line activation circuit and a redundant word line activation circuit and/or a redundant bit line acitvation circuit A word line activation circuit having a temporary memory circuit for storing word line inactivation information for inactivating a word line of a defective memory cell, and an inactivation address sensing circuit for determining whether or not a redundant memory cel... | 08/24/2010 |
| 7760584 | Semiconductor memory device, semiconductor device, and data write method A semiconductor memory device includes an output buffer which outputs an enable signal which makes an external memory device operable, an address buffer which generates an address at which data is held in the external memory device, an input buffer which receives th... | 07/20/2010 |
| 7742359 | Calibration circuit of a semiconductor memory device and method of operating the same A calibration circuit for a semiconductor device and a method of driving the same. The calibration circuit includes a PRBS generator in which a data pattern is generated within an integrated circuit without receiving data from the outside, a PRBS tester that compare... | 06/22/2010 |
| 7733737 | Semiconductor memory device using bus inversion scheme A semiconductor memory device is capable of transferring address signals at high speed and improving the operation reliability even though an input rate of an address signal increases, and thus a degradation of an operation speed caused by applying a bus inversion s... | 06/08/2010 |
| 7715270 | Address synchronous circuit capable of reducing current consumption in DRAM An address synchronous circuit includes an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of ... | 05/11/2010 |
| 7710816 | Memory access circuit A memory access circuit is provided. The memory access circuit includes a latch circuit, a feedback reset circuit, and a gate latch circuit. The latch circuit receives a high level input signal and outputs a first signal. The feedback reset circuit generates a secon... | 05/04/2010 |
| 7701801 | Programmable pulsewidth and delay generating circuit for integrated circuits A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse ... | 04/20/2010 |
| 7697368 | Semiconductor memory device and method of inputting addresses therein A semiconductor memory device is capable of reducing a test time by sharing input pins of addresses for the test, thereby reducing test costs also. The semiconductor memory device includes first and second address buffer units. The first address buffer unit is confi... | 04/13/2010 |
| 7675810 | Semiconductor memory device An internal signal generator for use in a semiconductor memory device includes an internal read address generation unit and an internal write address generation unit. The internal read address generation unit generates a plurality of read delay addresses by delaying... | 03/09/2010 |
| 7675809 | Memory compiler redundancy An improved redundancy architecture for embedded memories in an ASIC chip includes one or more compiler-generated embedded memory instances. Each embedded memory instance has a universal register for storing an address of a defective subunit of the memory instance f... | 03/09/2010 |
| 7672190 | Input latch circuit and method A circuit and method are provided that eliminate race conditions in data storage devices. Generally, the circuit includes: (i) an input latch to which an address signal (ADD) is applied; (ii) a multiplexer (MUX) to which the ADD is coupled from the input latch and t... | 03/02/2010 |
| 7652948 | Nonvolatile memory devices and programming methods using subsets of columns Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify ... | 01/26/2010 |
| 7623407 | Semiconductor device A semiconductor device which continuously outputs data in synchronism with a first clock includes a clock generator which generates a second clock from the first clock which is externally supplied, a flip-flop circuit which operates in synchronism with the second cl... | 11/24/2009 |
| 7616521 | Semiconductor memory device selectively enabling address buffer according to data output A semiconductor memory device can reduce needless current consumption when addresses are inputted. A semiconductor memory device includes a clock enable buffering unit for receiving a clock enable signal to output a buffer enable signal, an address buffer control un... | 11/10/2009 |
| 7613069 | Address latch circuit of semiconductor memory device An address latch circuit of a semiconductor memory device is provided. The address latch circuit includes a first address latch part, which latches a first address signal fed from outside according to a first address latch signal and outputs a second address signal.... | 11/03/2009 |
| 7609582 | Branch target buffer and method of use A branch target buffer (BTB) storing a data entry related to a branch instruction is disclosed. The BTB conditionally enables access to the data entry in response to a word line gating circuit associated with a word line in the BTB. The word line gating circuit stor... | 10/27/2009 |
