Class 365/230.03 - Plural blocks or banks

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter in which the memory elements are arranged
No. of patents: 4618
Last issue date: 05/29/2012

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Number	Title	Issue Date
8189422	Semiconductor device and semiconductor system having the same A semiconductor device according to example embodiments may be configured so that, when a read command for performing a read operation is input while a write operation is performed, and when a memory bank accessed by a write address during the write operation is the...	05/29/2012
8189423	256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. In certain of the gap cells, multiplexers are provided ...	05/29/2012
8184500	Semiconductor memory device and method for operating the same A semiconductor memory device includes a plurality of banks, a first bank selection driving control signal generation unit configured to generate a plurality of first bank selection driving control signals corresponding to the plurality of banks in response to an ac...	05/22/2012
8169849	Memory system and method with serial and parallel modes Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links o...	05/01/2012
8164970	Third dimensional memory with compress engine An integrated circuit and method for modifying data by compressing the data in third dimensional memory technology is disclosed. In a specific embodiment, an integrated circuit is configured to perform compression of data disposed in third dimensional memory. For ex...	04/24/2012
8159898	Architecture of highly integrated semiconductor memory device A semiconductor memory device includes: a first row control circuit region corresponding to a first memory bank; a first column control circuit region corresponding to the first memory bank; a second row control circuit region corresponding to a second memory bank a...	04/17/2012
8149643	Memory device and method A memory device and method may include separating alternating read and write accesses to different banks of a memory device. ...	04/03/2012
8134884	Semiconductor memory device A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank ...	03/13/2012
8130582	Semiconductor signal processing device A unit operator cell includes a plurality of SOI (Silicon on Insulator) transistors, write data is stored in a body region of at least two SOI transistors, and the storage SOI transistors are connected in series with each other to a read port or each of the storage ...	03/06/2012
8120985	Multi-bank memory device method and apparatus In one embodiment, a memory device comprises a semiconductor substrate, a first set of memory banks disposed on the semiconductor substrate and a second set of memory banks disposed on the semiconductor substrate. Each memory bank of the second set is split into a p...	02/21/2012
8116164	Semiconductor memory device A semiconductor memory device includes a plurality of banks; a peripheral circuit configured to send data to and receive data from the plurality of banks; and data lines configured to connect the plurality of banks and the peripheral circuit, wherein the plurality o...	02/14/2012
8116154	Semiconductor memory device with a write control circuit commonly provided for a plurality of pages To provide a plurality of write amplifiers that perform a data write operation upon memory cells and a write control circuit that controls a timing of a data write operation performed by the write amplifiers. When a data write operation using another write amplifier...	02/14/2012
8068380	Block repair scheme Systems, memory arrays and methods (e.g., methods of block repair) are provided. One such system includes a memory array including a memory bank including a plurality of sections, wherein each of the plurality of sections includes at least one redundant row. Further...	11/29/2011
8068379	Dynamic RAM A plurality of sub word lines each have a length equivalent to the division of a main word line along the extension direction thereof, arranged along a bit line crossing said main word line, and are connected with a plurality of memory cells. A first sub word select...	11/29/2011
8064282	Method of accessing synchronous dynamic random access memory, memory control circuit, and memory system including the same An access area is set within an address space of a dynamic random access memory by arranging two or more complete columns of blocks, in which blocks of memory cells are arranged within an entirety of a specified range of row addresses, along a direction of column ad...	11/22/2011
8064284	Method for accessing vertically stacked embedded non-flash re-writable non-volatile memory A multiple-type memory is disclosed. The multiple-type memory includes memory blocks in communication with control logic blocks. The memory blocks and the control logic blocks are configured to emulate a plurality of memory types. The memory blocks can be configured...	11/22/2011
8064283	Semiconductor memory apparatus and a method for reading data stored therein A semiconductor memory apparatus includes a data bus inversion (DBI) section configured to receive a plurality of input data and decide whether to invert or output, without an inversion, the plurality of input data depending upon logic levels of the plurality of dat...	11/22/2011
8054710	Integrated circuit device and electronic instrument An integrated circuit device includes first to Nth circuit blocks CB1 to CBN, a first interface region disposed along a fourth side and on the D2 side of the first to Nth circuit blocks CB1 to CBN, and a second interface region disposed along a ...	11/08/2011
8050131	System and memory for sequential multi-plane page memory operations A system and method for performing memory operations in a multi-plane flash memory. Commands and addresses are sequentially provided to the memory for memory operations in memory planes. The memory operations are sequentially initiated and the memory operation for a...	11/01/2011
8036049	Semiconductor memory device including a global input/output line of a data transfer path and its surrounding circuits A semiconductor memory device includes an input/output line of a data transfer path and its surrounding circuits, comprising a controller which generates a control signal corresponding to command and address input in read and write operation; and a repeater which se...	10/11/2011
8036061	Integrated circuit with multiported memory supercell and data path switching circuitry An integrated circuit. The integrated circuit includes a plurality of memory requesters and a memory supercell. The memory supercell includes a plurality of memory banks each of which forms a respective range of separately addressable storage locations, wherein the ...	10/11/2011
8027209	Continuous programming of non-volatile memory A non-volatile storage system connects a signal driver to a first control line that is connected to a first non-volatile storage element, charges the first control line using the signal driver while the signal driver is connected to the first control line, disconnec...	09/27/2011
RE42659	Large-capacity semiconductor memory with improved layout for sub-amplifiers to increase speed A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells locate...	08/30/2011
8009503	Card controller controlling semiconductor memory including memory cell having charge accumulation layer and control gate A card controller includes an arithmetic processing device. The controller writes data to a semiconductor memory having a first memory block and a second memory block each including a plurality of nonvolatile memory cells each configured to hold at least 2 bits, dat...	08/30/2011
8004926	System and method for memory array decoding A memory system includes Q memory blocks that each include M memory sub-blocks. The memory system also includes Q word line decoders that each are associated with a different one of the Q memory blocks. The memory system also includes a bit line decoder and Q×M swi...	08/23/2011
7995419	Semiconductor memory and memory system A semiconductor memory that assigns M data groups, each data group including N data, to a first address, where M and N are integers equal to or larger than 2; and wherein L data among N data is designated by a second address indicating a position of the data groups ...	08/09/2011
7995420	User selectable banks for DRAM A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. M...	08/09/2011
7990798	Integrated circuit including a memory module having a plurality of memory banks An integrated circuit including a memory module having a plurality of memory banks is disclosed. One embodiment provides an even number of at least four memory banks. Each memory bank has a plurality of memory cells. Each two of the memory bank form a memory bank re...	08/02/2011
7969810	256 Meg dynamic random access memory A 256 Meg dynamic random access memory is comprised of a plurality of cells organized into individual arrays, with the arrays being organized into 32 Meg array blocks, which are organized into 64 Meg quadrants. Sense amplifiers are positioned between adjacent rows i...	06/28/2011
7965575	Semiconductor memory device and method of providing product families of the same A semiconductor memory device includes a plurality of banks, a plurality of data input/output terminals, control signal terminals, address signal terminals, and at least one or a plurality of virtual chips, each of which has the banks grouped together, thereby being...	06/21/2011
7957215	Method and apparatus for generating temperature-compensated read and verify operations in flash memories Methods and an apparatuses for generating a word-line voltage are disclosed. A word-line voltage generator includes a first current source, an adjustable current source, adjustable current sink, and a voltage converter, all operably coupled to a current sum node. Th...	06/07/2011
7957217	Method of controlling internal voltage and multi-chip package memory prepared using the same The invention relates generally to a multi-chip package (MCP) memory device, and more particularly, but without limitation, to a MCP memory device having a reduced size. In one embodiment, the MCP memory device includes: a transfer memory chip; and a plurality of me...	06/07/2011
7957216	Common memory device for variable device width and scalable pre-fetch and page size Embodiments of the invention are generally directed to systems, methods, and apparatuses for a common memory device for variable device width and scalable pre-fetch and page size. In some embodiments, a common memory device (such as a DRAM) can operate in any of a n...	06/07/2011
7952943	Semiconductor memory device having low power consumption type column decoder and read operation method thereof The present invention relates to a semiconductor memory device having a low power consumption type column decoder and read operation method thereof. In accordance with the semiconductor memory device and read operation method thereof according to the present inventi...	05/31/2011
7944773	Synchronous command-based write recovery time auto-precharge control Methods of operating a memory device and memory devices are provided. For example, a method of operating a memory array is provided that includes a synchronous path and an asynchronous path. A Write-with-Autoprecharge signal is provided to the synchronous path, and ...	05/17/2011
7940597	Semiconductor memory device and parallel test method of the same Semiconductor memory device and parallel test method of the same. The test includes writing data into multiple memory banks simultaneously, reading the data from a portion of the memory banks, compressing the read data and outputting the compressed data to the outsi...	05/10/2011
7940598	Integrated circuit memory device, system and method having interleaved row and column control An integrated circuit memory device, system and method embodiments decode interleaved row and column request packets transferred on an interconnect at a first clock frequency. Separate row decode logic and column decode logic, clocked at a relatively slower second c...	05/10/2011
7916572	Memory with addressable subword support Integrated circuits are provided that have memory arrays. The memory arrays may include rows and columns of data byte storage locations. To implement algorithms that that process data subwords, a memory array may be partitioned into individual memory banks each of w...	03/29/2011
7916570	Low power memory device In a memory device having a memory core and a signal interface, receiving a command that specifies at least a portion of a memory access. During the memory access, transferring data between the memory core and the signaling interface, and transferring the data betwe...	03/29/2011
7916571	Apparatus for implementing multiple integrated circuits using different gate oxide thicknesses on a single integrated circuit die An apparatus comprising plurality of functional integrated circuit blocks, each manufactured with different oxide thicknesses on a monolithic integrated circuit die, is described. Using different gate oxide thicknesses for different functional integrated circuit blo...	03/29/2011

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Class 365/230.03 - Plural blocks or banks