Class 365/230.01 - ADDRESSING

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter including selection of a memory location.
No. of patents: 1087
Last issue date: 05/22/2012

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Number	Title	Issue Date
6903744	Graphics processing system A system is provided for storing pixel data associated with a predetermined pixel region. The system is configured to store pixel data in a predetermined block of memory along with a fill check bit indicative of whether or not values for each pixel within the pixel ...	06/07/2005
6898662	Memory system sectors An embodiment of the present invention includes a method of implementing the logical grouping of memory system sectors in a non-volatile memory system in order to increase the operational speed of the memory system, the method comprising allocating sets of contiguou...	05/24/2005
6888777	Address decode Machine-readable media, methods, and apparatus are described which process memory transactions. In some embodiments, a processor or other external components provide a memory controller with decoded memory addresses. The memory controller then may access the memory ...	05/03/2005
6882558	Ferroelectric-type nonvolatile semiconductor memory and operation thereof A method of operating a ferroelectric-type nonvolatile semiconductor memory comprising a memory unit having a bit line, a transistor for selection, a sub-memory unit composed of memory cells that are M in number, plate lines that are M in number, and a sense amplifi...	04/19/2005
6879718	Efficient method and system for determining parameters in computerized recognition In computerized recognition having multiple experts, a method and system is described that obtains an optimum value for an expert tuning parameter in a single pass over sample tuning data. Each tuning sample is applied to two experts, resulting in scores from which ...	04/12/2005
6874058	Content addressed memories A content addressable memory comprises a CAM control logic unit and plural cells connected in a chain. Each cell comprises a memory block coupled to a common address bus, a comparator coupled to a common data bus and to the data interface of the memory block. A swit...	03/29/2005
6870787	Configuration and method for checking an address generator In a configuration for checking an address generator, a memory apparatus is configured such that it can store values of address signals that are present on lines of an address bus. The stored values can then be output to at least one access point where the values ar...	03/22/2005
6871254	Processor and storage apparatus An operating unit operates candidate operation data Da, Db. The candidate operation data Da, Db are contained in two source memories, respectively, or alternatively in one of the two source memories. An address-generating unit generates an address signal Aa and read...	03/22/2005
6868030	Semiconductor memory apparatus simultaneously accessible via multi-ports A dual-port semiconductor memory apparatus constructed by a core circuit and a plurality of ports, different row blocks of which in the same column block of the core circuit are simultaneously accessible. Since each of the ports is provided with a global data bus, d...	03/15/2005
6865133	Memory circuit with redundant configuration A memory circuit has a plurality of blocks which further comprises a plurality of regular sectors and a spare sector, wherein each sector further comprises a plurality of memory cells, and when a regular sector in a first block is defective, this defective regular s...	03/08/2005
6862247	Pseudo-static synchronous semiconductor memory device For a pseudo-SRAM (Static Random Access Memory) macro operating in synchronization with a clock signal, a page operation instructing signal instructing a page operation and a page close instructing signal instructing completion of the page operation are prepared as ...	03/01/2005
6859398	Semiconductor memory component A plurality of digital-analog converters and analog-digital converters are connected in the data lines between the connection contacts and the memory cells of a memory device. The memory can be read, written to and actuated by analog data transfers instead of the pr...	02/22/2005
6856571	Memory system, method and predecoding circuit operable in different modes for selectively accessing multiple blocks of memory cells for simultaneous writing or erasure A memory system including a non-volatile flash memory and a method for simultaneously selecting a plurality of memory blocks are disclosed. The memory system is organized into multiple main blocks each having multiple smaller blocks, emulating a disk drive. Control ...	02/15/2005
6847573	Synchronous SRAM-compatible memory device including DRAM array with internal refresh The synchronous SRAM-compatible memory includes a DRAM array, a data input/output unit, an address input unit, a burst address generating unit, a state control unit, a refresh timer, and a refresh control unit. The data input/output unit controls input and output of...	01/25/2005
6842394	Semiconductor device using SCL circuit A high-speed, reduced power consumption address decoder circuit, wherein a decoder control signal Φ2 is rendered unnecessary between an address buffer control signalΦ1 and the decoder control signal Φ2, thereby implementing speed-up in operation of a decoder circ...	01/11/2005
6842398	Multi-mode synchronous memory device and methods of operating and testing same A synchronous semiconductor memory device is operable in a normal mode and an alternative mode. The semiconductor device has a command bus for receiving a plurality of synchronously captured input signals, and a plurality of asynchronous input terminals for receivin...	01/11/2005
6842362	Magnetic random access memory One end of a write word line is connected to a decoder/driver unit. The decoder/driver unit is constituted by a P channel MOS transistor, an N channel MOS transistor, a differential amplifier, and an NAND circuit. When WRITE, CHRDY and RA1 all become “H”,...	01/11/2005
6839807	Multi-way set associative cache memory A multi-way set associative cache memory includes a set selection signal operating a sense amplifier. In reading data stored in a set, a set selection signal enables the sense amplifier to select one of sets while plural sets are active by a row address. The simplif...	01/04/2005
6839300	Refresh controller and address remapping circuit and method for dual mode full/reduced density DRAMs A dual mode, full density/half density SDRAM includes a refresh controller specifically adapted to refresh memory cells of the SDRAM in the half density mode at a rate that is significantly slower than the rate at which the memory cells are refreshed in the full den...	01/04/2005
6836441	Apparatus of repairing memory cell and method therefor The present invention provides a semiconductor memory cell repairing apparatus and method that can effectively repair memory cells although a various type of failures in memory cells are generated when a rule in the failure is detected. There is provided a me...	12/28/2004
6834023	Method and apparatus for saving current in a memory device A memory device is configured to conserve electrical current by disabling the address lines provided to a memory bank when the address is not needed, such as during periods of automatic precharge. Because address data need not be provided while the bank is in an aut...	12/21/2004
6834020	Semiconductor storage device A semiconductor memory device is provided which operates according to the specification of an SRAM, and which is capable of making the memory cycle shorter than heretofore, without normal access being delayed by the influence of refresh. An ATD circuit (4) re...	12/21/2004
6831873	Independent in-line SDRAM control A device and method for independent control of SDRAM memory in an SDRAM memory module. The device includes an in-line controller (ILC) coupled to receive indications of memory controller interrupt events. The ILC is coupled with the SDRAM memory, possibly through a ...	12/14/2004
6829181	Semiconductor memory, method of testing semiconductor memory, and method of manufacturing semiconductor memory Testing circuits each including a comparator for comparing data read from semiconductor memories to be tested with expected value data and thereby detecting coincidences/non-coincidences, and a counter for counting the number of non-coincidences detected are provide...	12/07/2004
6826112	Low power logic gate The invention includes a logic gate. The logic gate includes a charge holding device. A charging circuit selectively provides a predetermined charge for the charge holding device. A logic gate output is a function of charge on the charge holding device. The logic ga...	11/30/2004
6826657	Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory system comprising a memory module and a memory controller. The memory modu...	11/30/2004
6822887	Semiconductor circuit device with mitigated load on interconnection line A transistor region for defining a transistor receiving an address signal at a gate thereof is provided in or near a region below an address interconnection line transmitting a corresponding address signal. The corresponding address signal and the gate electrode of ...	11/23/2004
6809947	Multi-level semiconductor memory architecture and method of forming the same An array block has at least two sub-array blocks and a first interconnect routing channel through which a first group of local interconnect lines extend. Each of the two sub-array blocks includes at least two lower-level sub-array blocks and a second interconnect ro...	10/26/2004
6807126	Semiconductor memory device and electronic information device using the same In a semiconductor memory device for performing a memory operation by controlling an internal voltage and a memory operation voltage, a cycle of an internal clock signal is varied in accordance with operation time characteristics of the memory operation. ...	10/19/2004
6807125	Circuit and method for reading data transfers that are sent with a source synchronous clock signal A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit ...	10/19/2004
6804162	Read-modify-write memory using read-or-write banks Minimal memory access times are realized by using a single access to a read-modify-write bank. A read-modify-write memory including at least one read-or-write bank is operated in a manner that uses at most one access to each of the at least one read-or-write banks f...	10/12/2004
6804158	Semiconductor circuit device with improved special mode In a DRAM employing a shared sense amplifier method, a bit line select signal falls to the level of ground potential after a potential difference is generated between a pair of bit lines and sense nodes in response to activation of a word line in a self refresh mode...	10/12/2004
6801979	Method and apparatus for memory control circuit A method and circuit for fast memory access (read or write) of the data to and from a memory array is disclosed. Architecture wise, the memory array control circuit provides for at least two address latches and two page registers. The first address latch contains a ...	10/05/2004
6801471	Fuse concept and method of operation It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires tha...	10/05/2004
6798711	Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of...	09/28/2004
6798420	Video and graphics system with a single-port RAM A video and graphics system has an input for receiving compressed video data and an input for receiving graphics data. The compressed video data may include HDTV video and/or SDTV video, and may be included in compressed data streams such as an MPEG-2 Transport stre...	09/28/2004
6791896	Semiconductor memory device capable of changing an address space thereof The state of a prescribed internal column address signal bit is selectively fixed according to a mode switch circuit. A specific row address signal bit is transmitted instead of a column address signal bit under the control of the mode switch circuit. Thus, a semico...	09/14/2004
6791898	Memory device providing asynchronous and synchronous data transfer Embodiments of the present invention provide a memory device having multiple modes of data transfer. In one embodiment, async/sync logic and a configuration register provide for asynchronous and synchronous data transfer. The async/sync logic utilizes the configurat...	09/14/2004
6788609	Storage device employing a flash memory A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of errors in the ...	09/07/2004
6788617	Device for generating memory address and mobile station using the address for writing/reading data A device for generating memory addresses is provided that is suitable for generating memory addresses transposed in row/column directions with reference to a data successively stored therein along with a mobile station by using the same, and a method for writing/rea...	09/07/2004

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Class 365/230.01 - ADDRESSING