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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 7350018 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the ... | 03/25/2008 |
| 7350016 | High speed DRAM cache architecture A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memor... | 03/25/2008 |
| 7345936 | Data storage circuit A data storage circuit having a plurality of memory cells (S1), a plurality of bit lines (BL, /BL) and a precharge circuit further comprises a discharge circuit. In an operating mode of the data storage circuit, the bit lines (BL, /BL) are precharged by the p... | 03/18/2008 |
| 7340364 | Test apparatus, and control method There is provided a test apparatus that tests a device under test. The test apparatus includes a control processor that executes a test program for testing the device under test, a test unit that is connected to the device under test and tests the device under test ... | 03/04/2008 |
| 7340486 | System and method for file system snapshot of a virtual logical disk A system and method generates a consistent file system snapshot of a virtual logical disk (VLD). The system and method ensures that database files are stored on the VLD are consistent at the time a snapshot is generated by first flushing all buffers and then blockin... | 03/04/2008 |
| 7336558 | Semiconductor memory device with reduced number of pads A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a secon... | 02/26/2008 |
| 7333372 | Reset circuit and integrated circuit device with reset function A reset circuit, which generates a reset signal for initializing an internal circuit of an integrated circuit device having an auto-loading function, includes a first register which stores a predetermined expected value data; a second register holding data which was... | 02/19/2008 |
| 7333378 | Memory device that recycles a signal charge A semiconductor memory device having a shared sense amplifier architecture includes a bitline equalizing voltage generator, which recycles a boost voltage to generate bitline equalizing voltage. The bitline equalizing voltage is used to generate signals for activati... | 02/19/2008 |
| 7334078 | Method and system for handling streaming information One aspect of the present invention leads to a method of handling streaming information. The method includes receiving the streaming information and analyzing the streaming information to locate one or more points of interest in the streaming information. An index o... | 02/19/2008 |
| 7327618 | Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low... | 02/05/2008 |
| 7326594 | Connecting a plurality of bond pads and/or inner leads with a single bond wire An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least tw... | 02/05/2008 |
| 7324364 | Layout techniques for memory circuitry An integrated circuit includes memory circuitry with a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the s... | 01/29/2008 |
| 7324367 | Memory cell and method for forming the same A semiconductor memory cell structure having 4 F2 dimensions and method for forming the same. The memory cell is formed on a surface of a substrate and includes an active region formed in the substrate, a semiconductor post formed on the surface of the su... | 01/29/2008 |
| 7321520 | Configurable length first-in first-out memory A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for... | 01/22/2008 |
| 7319606 | Memory A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array ... | 01/15/2008 |
| 7317655 | Memory cell array biasing method and a semiconductor memory device A method of biasing a memory cell array during a data writing operation and a semiconductor memory device are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells in which a first terminal of a memory cell is ... | 01/08/2008 |
| 7315479 | Redundant memory incorporating serially-connected relief information storage A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in seri... | 01/01/2008 |
| 7310260 | High performance register accesses The use of a bus clock is eliminated in communication between a cpu, or mpu, and a register block. The communication between the cpu/mpu and the register block is made combinatorial, such that the cpu/mpu does not require any acknowledge or wait signal from the regi... | 12/18/2007 |
| 7310257 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit ... | 12/18/2007 |
| 7301828 | Decoding techniques for read-only memory A memory circuit includes a number of bit line structures, each including at least three bit lines; a number of word lines that intersect with the bit line structures at a number of sites; and a number of switching devices located at the sites. A number of column se... | 11/27/2007 |
| 7301824 | Method and apparatus for communication within an integrated circuit Method and apparatus for communication within an integrated circuit is described. In one example, an integrated circuit includes a first logic circuit, a second logic circuit, first first-in-first-out (FIFO) logic, second FIFO logic, and an interconnection network. ... | 11/27/2007 |
| 7295481 | Power saving by disabling cyclic bitline precharge A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is... | 11/13/2007 |
| 7289384 | Method for writing to multiple banks of a memory device In a multi-bank memory system such as a synchronous dynamic random access memory (SDRAM), a method of writing data to the banks is provided. This method allows for writing to any number of banks. More particularly, this method allows for writing to a selected number... | 10/30/2007 |
| 7290117 | Memory having increased data-transfer speed and related systems and methods A memory includes an address bus, address counter, address decoder, comparator, and control circuit. During a data read or write cycle, the address bus receives an external address, the address counter generates an internal address, which the address decoder decodes... | 10/30/2007 |
| 7286414 | Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Memory states of a multi-bit memory cell are demarcated by generating read reference signals having levels that constitute boundaries of the memory states. The read reference signals may be dependent upon the levels of programming reference signals used for controll... | 10/23/2007 |
| 7287115 | Multi-chip package type memory system A multichip package type memory system is disclosed, which comprises a plurality of types of memory integrated circuits which are provided in a memory system in a package having an internal bus, and accessed from exterior of the package and/or within the package, an... | 10/23/2007 |
| 7283380 | Content addressable memory with selective error logging A content addressable memory (CAM) device with selective error logging. The CAM device includes a CAM array and an error detection circuit coupled to receive a data value from a selected storage location within the CAM array, the error detection circuit being adapte... | 10/16/2007 |
| 7283409 | Data monitoring for single event upset in a programmable logic device Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators... | 10/16/2007 |
| 7274585 | Methods of operating integrated circuit memory devices Methods of operating an integrated circuit memory device include providing a first address and a first command to the memory device and executing the first command within the memory device. This step of executing the first command is performed concurrently with prov... | 09/25/2007 |
| 7275130 | Method and system for dynamically operating memory in a power-saving error correcting mode A scrubbing controller used with a DRAM stores data in an error correcting code format. The system then uses a memory control state machine and associated timer to periodically cause the DRAM to read the error correcting codes. An ECC generator/checker in the scrubb... | 09/25/2007 |
| 7265926 | High speed hard disk drive with symmetric writer A disk drive data storage system, comprising a magnetic disk a head for writing data to the disk, and circuitry for providing a first voltage (HWX) to a first node (N1) and a second voltage (HWY) to a second node (N2). The first and second volt... | 09/04/2007 |
| 7266075 | Recording medium with a linking area including scrambling data thereon and apparatus and methods for forming, recording, and reproducing the recording medium A recording medium, such as a high-density and/or read-only recording medium including a data area including at least two data sections and a linking area to link neighboring data sections, the linking area including scrambled user data produced by scrambling user d... | 09/04/2007 |
| 7266038 | Method for activating and deactivating electronic circuit units and circuit arrangement for carrying out the method The invention provides an electronic circuit arrangement having an electronic circuit module (100) constructed from one or more electronic circuit units (101a-101n), a select signal generating unit (105) for generating a sel... | 09/04/2007 |
| 7259980 | Memory A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array ... | 08/21/2007 |
| 7257075 | Recording medium with a linking area thereon and apparatus and methods for forming, recording, and reproducing the recording medium A recording medium, such as a high-density and/or read-only recording medium that has the same or similar physical recording format, including a linking area, in order to improve reproduction compatibility with a high-density and/or rewritable recording medium, and ... | 08/14/2007 |
| 7257034 | Semiconductor integrated circuit device There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is ... | 08/14/2007 |
| 7257045 | Uni-stage delay speculative address decoder An address decoder. The address decoder includes a plurality of decoder circuits. Each decoder circuit includes a first stage including a first logic circuit having n−1 inputs, the n−1 inputs being a subset of n inputs conveyed to each decoder circuit. Each deco... | 08/14/2007 |
| 7253057 | Memory cell with reduced size and standby current A present invention is a method, and resulting device, for fabricating memory cells with an extremely small area and reduced standby current. The small area is accomplished by a judicious use of spacers which allows a tunnel window of a storage device to be fabricat... | 08/07/2007 |
| 7254690 | Pipelined semiconductor memories and systems The invention describes and provides pipelining of addresses to memory products. Addresses are pipelined to multibank memories on both rising and falling edges of a clock. Global Address Supervisor pipelines these addresses optimally without causing bank or block or... | 08/07/2007 |
| 7254089 | Memory with selectable single cell or twin cell configuration A memory circuit comprises a memory including a memory array, a twin cell mode predecoder, and a row address predecoder. The memory array comprises word lines. The twin cell mode predecoder is configured for selecting one of four word line activation configurations ... | 08/07/2007 |
