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"During my service in the United States Congress, I took the initiative in creating the Internet."
Al Gore ; The basis for the later misquote by US Republicans that Gore had "invented" the Internet. Gore was the leading political champion of the modern-day Internet.
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| Number | Title | Issue Date |
| 6650593 | Memory system having memory controller for controlling different types of memory chips A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory ... | 11/18/2003 |
| 6646917 | Storage device managing nonvolatile memory by converting logical address to physical address of nonvolatile memory A flash memory includes a user block for storage of user data, an alternate block reserved for substitution, a conversion table for storage of a physical address of the user block corresponding to a logical address, and an alternate table for storage of a... | 11/11/2003 |
| 6643195 | Self-healing MRAM An MRAM device includes an array of memory cells. A plurality of traces cross the memory cells. An address decoder coupled to the plurality of traces decodes an address and selects a corresponding subset of the traces. A sparing circuit coupled to the add... | 11/04/2003 |
| 6636454 | Low-power consumption semiconductor memory device A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. I... | 10/21/2003 |
| 6633508 | Semiconductor memory device and memory system Two memory cells in different memory arrays are simultaneously selected in accordance with the designation of a specific write operation mode to associate a logic 1 of a write signal with a state in which an electric charge exists in each capacitor. Furth... | 10/14/2003 |
| 6618315 | Non-volatile, electrically alterable semiconductor memory Non-volatile, electrically alterable semiconductor memory, including at least one two-dimensional array of memory cells with a plurality of rows and a plurality of columns, column selection circuitry for selecting columns among the plurality of columns, a... | 09/09/2003 |
| 6614709 | Method and apparatus for processing commands in a queue coupled to a system or memory A queue, either in software or hardware, with a plurality of layers with each layer having a plurality of locations. The queue receives a command, and compares the command with the pending commands in the queue to determine if the command should be proces... | 09/02/2003 |
| 6611474 | Semiconductor device A semiconductor device to output voltages at three levels to a word driver while alleviating the breakdown voltage in the MOS transistor. This invention is comprised of a breakdown-voltage reducing MOS transistor inserted in the word driver and two NMOS t... | 08/26/2003 |
| 6603694 | Dynamic memory refresh circuitry A circuit for refreshing data stored in an array of dynamic memory cells is provided. The circuit includes an integrated circuit chip. The chip has the array of memory cells formed thereon. The circuit also includes a refresh rate analysis circuit for det... | 08/05/2003 |
| 6597627 | Clock switching circuitry for avoiding conflict of data handling occuring in a memory Clock switching circuitry includes a memory having a plurality of storage locations of a particular address each and configured to allow data to be written in and read out at the same time. The circuitry further includes a write pointer, a read pointer, a... | 07/22/2003 |
| 6594818 | Memory architecture permitting selection of storage density after fabrication of active circuitry A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a ... | 07/15/2003 |
| 6594738 | Semiconductor device in which MPU and DRAM as secondary cache memory are mounted on same chip to easily realize high speed of cycle time under restriction on chip size A semiconductor device includes an MPU (Micro Processing Unit) section, a DRAM (Dynamic Random Access Memory) section, a plurality of address registers, and a plurality of address delay compensating units. The MPU section is provided on a chip to output a... | 07/15/2003 |
| 6594183 | Wear leveling techniques for flash EEPROM systems A mass storage system made of flash electrically erasable and programmable read only memory ("EEPROM") cells organized into blocks, the blocks in turn being grouped into memory banks, is managed to even out the numbers of erase and rewrite cycles experien... | 07/15/2003 |
| 6594710 | Apparatus and method for a random access peripheral unit In a data processing system, the ability to provide indirect addressing capability is implemented by providing a peripheral system having a first memory unit, second memory unit, and a control unit. In a first embodiment of the invention, a first address ... | 07/15/2003 |
| 6589187 | Prioritized dynamic memory allocation of arrhythmia episode detail collection A software system implemented in a medical device includes an allocation scheme for allocating storage of cardiac data. The software system enables storing cardiac data in a plurality of addressable locations. When all available locations within the plura... | 07/08/2003 |
| 6580659 | Burst read addressing in a non-volatile memory device A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory... | 06/17/2003 |
| 6574162 | Semiconductor memory device utilizing access to memory area located outside main memory area A semiconductor memory device is provided. The semiconductor memory device includes a primary memory area including a plurality of memory blocks arranged in rows and columns, the plurality of memory blocks including a predetermined memory block; a seconda... | 06/03/2003 |
| 6570793 | Semiconductor memory having a redundancy circuit for word lines and method for operating the memory A redundancy circuit for a semiconductor memory having word lines and redundant word lines is described. The redundancy circuit activates the word line at the same time as checking to determine whether the applied address per word line is the address of a... | 05/27/2003 |
| 6570808 | Apparatus for selecting bank in semiconductor memory device An apparatus for selecting banks in a semiconductor memory device provides a half-chip by adjusting all bits including the most significant bit (MSB) of bank addresses to select normal banks even if degraded banks are included in both upper and lower bank... | 05/27/2003 |
| 6570800 | High speed clock synchronous semiconductor memory in which the column address strobe signal is varied in accordance with a clock signal The column address strobe signal (CAS) which is changed in cycles as many as a plurality of times that of a clock signal cycle is input to the memory block (MBK0 to MBKn). A plurality of serial data readout from the memory cell array (10) and parallel/ser... | 05/27/2003 |
| 6567336 | Semiconductor memory for logic-hybrid memory This invention provides ways to intercept abnormal power signals to prevent damaging the memory in a semiconductor. To achieve this, the semiconductor memory comprises a first control signal line controlling a selection from row addresses, a second contro... | 05/20/2003 |
| 6567334 | Storage device employing a flash memory A semiconductor disk wherein a flash memory into which data is rewritten in block unit is employed as a storage medium, the semiconductor disk including a data memory in which file data are stored, a substitutive memory which substitutes for blocks of err... | 05/20/2003 |
| 6564331 | Low power register file A mechanism is provided for reducing the power consumption of a register file by disabling unused register file read ports. A selected entry of the register file is hardwired to zero and the address of the selected entry is driven to the address decoder o... | 05/13/2003 |
| 6563732 | Redundancy circuit and method for flash memory devices A method and circuit are disclosed for replacing defective columns of flash memory cells in flash memory device. The circuit includes a plurality of sets of storage elements, each set of storage elements being capable of identifying at least one column of... | 05/13/2003 |
| 6552950 | Nonvolatile semiconductor memory device having changeable spare memory address A nonvolatile semiconductor memory device comprising a main memory cell array and a spare memory cell array, capable of freely accessing data in the spare memory cell array irrespective of the physical addresses of the spare memory cell array, and a metho... | 04/22/2003 |
| 6549468 | Non-volatile memory with address descrambling A flash memory has been described that can be coupled to an SDRAM controller that performs address scrambling. The flash memory includes a programmable address de-scrambler. The de-scrambler can be programmed to de-scramble primarily row addresses, includ... | 04/15/2003 |
| 6542428 | Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area A column select gate of a semiconductor memory device includes read gate circuits. Each read gate circuit includes read gate transistors. Each read gate transistor connects a read column select line to a global I/O line pair in response to a potential lev... | 04/01/2003 |
| 6542430 | Integrated memory and memory configuration with a plurality of memories and method of operating such a memory configuration A memory configuration has at least two memories connected to one another. In the event of a memory cell access, it is ascertained in a comparison circuit of the first memory whether the address applied to a first communications interface of the memory co... | 04/01/2003 |
| 6542435 | Method and apparatus for equalization of address transition detection pulse width A method and apparatus ensure equal address transition detection (ATD) pulse width for all address and chip enable transitions. Address buffer signals from one end of an integrated circuit are combined to form a first combined signal. Address buffer signa... | 04/01/2003 |
| 6538952 | Random access memory with divided memory banks and data read/write architecture therefor A dynamic random access memory with two divided memory banks is disclosed wherein memory cells are divided into first and second groups each of which includes an array of memory cells connected to a corresponding word line. Those memory cells are sub-divi... | 03/25/2003 |
| 6535950 | Semiconductor memory device having a refresh operation A semiconductor memory device, such as a DRAM, which needs to be refreshed for retaining data, is provided with a storing portion for storing data therein, and a busy signal outputting portion outputting a busy signal during the refresh operation.... | 03/18/2003 |
| 6535451 | Semiconductor memory A plurality of sense amplifier areas are placed alternately with respect to a plurality of memory array areas arranged along a first direction. The plurality of memory array areas are respectively provided with a plurality of bit lines provided along the ... | 03/18/2003 |
| 6535436 | Redundant circuit and method for replacing defective memory cells in a memory device A memory device having redundancy is disclosed. The memory device includes an array of memory cells organized into rows and columns of memory cells, each row of memory cells including a plurality of addressable memory cells and redundant memory cells, the... | 03/18/2003 |
| 6535412 | Semiconductor memory device capable of switching output data width In response to an output data width switching mode signal, a predecoder zone+selector zone outputs selection signals SEL0 to SEL7 and WORDA to WORDC to a preamplifier+write driver zone. The preamplifier+write driver zone can switch connection between glob... | 03/18/2003 |
| 6532179 | Input signal receiving circuit for semiconductor integrated circuit The semiconductor integrated circuit according to the present invention comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receivin... | 03/11/2003 |
| 6529427 | Test structures for measuring DRAM cell node junction leakage current A method and methodology is provided for measuring ultra-low leakage current in DRAM devices. The invention provides a method and structures that are not limited to a trade-off between the number of contact points that are established to do the measuremen... | 03/04/2003 |
| 6525986 | Stackable microelectronic components with self-addressing scheme A memory device particularly useful in size-constrained electronic products, such as cardiac stimulators. To provide additional memory for such size-constrained products, memory chips are stacked one on top of another. The memory chips are configured to f... | 02/25/2003 |
| 6525989 | Activation of word lines in semiconductor memory device To provide a technique for reducing the power consumption associated with word line activation in a semiconductor memory device. The semiconductor memory device is provided with a word line activation controller for controlling word line activation. Where... | 02/25/2003 |
| 6523084 | Data processing apparatus To provide a data processing apparatus that allows the occurrence of a gate disturb effect to be reduced and the reliability of data processing using the internal flash memory to be improved. A loop process section of a program stored in flash memory is h... | 02/18/2003 |
| 6522599 | Operable synchronous semiconductor memory device switching between single data rate mode and double data rate mode A synchronous semiconductor memory device operates an input/output buffer circuit in synchronization with an external clock signal in a single data rate SDRAM operation mode. In a double data rate SDRAM operation mode, an internal clock signal of a freque... | 02/18/2003 |
