Did You Know...
...Chester Carlson was a patent agent who tired of having to make multiple copies of patent applications using the only duplication method available at the time: carbon paper. In 1959 he came up with a new copying system and took it to IBM for evaluation. The "experts" at IBM determined potential sales to be only 5,000 units because people wouldn't want to use a bulky machine when they had carbon paper. Carlson's invention was the xerography process, the company founded on the system is Xerox.
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| Number | Title | Issue Date |
| 7369815 | Power collapse for a wireless terminal An integrated circuit for a modem processor includes processing units that are partitioned into “always-on” and “collapsible” power domains. An always-on power domain is powered on at all times. A collapsible power domain can be powered off if the processing... | 05/06/2008 |
| 7370220 | Method and apparatus for controlling power sequencing of a plurality of electrical/electronic devices A method and apparatus for managing power sequencing in a data storage system. The turn-on or spin-up sequence for the media drives in an array of media drives is selectively controlled such that the overall rush current is reduced. The individual drive components a... | 05/06/2008 |
| 7368960 | Circuit and method for monitoring the integrity of a power supply Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first met... | 05/06/2008 |
| 7365596 | State retention within a data processing system Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when ... | 04/29/2008 |
| 7366019 | Nonvolatile memory There is provided a non-volatile memory capable of being supplied with two varieties of externally supplied voltages, stabilizing the operation thereof, at a voltage in the vicinity of a threshold voltage for switching over between the externally supplied voltages, ... | 04/29/2008 |
| 7366036 | Memory device with control circuit for regulating power supply voltage A Local Dynamic Power Controller (LDPC) generates and deliver to a load a full swing voltage supply signal and a reduced swing voltage supply signal. Both the full and reduce voltage supply signals are generated from a single power supply. The full swing voltage sup... | 04/29/2008 |
| 7366048 | Bulk bias voltage level detector in semiconductor memory device There is provided a bulk bias voltage VBB level detector in a semiconductor memory device capable of improving tWR fail generated at a low temperature by compensating a temperature variance. The VBB level detector includes A bulk bias voltage level detector in a sem... | 04/29/2008 |
| 7366926 | On-chip supply regulators Integrated circuit chips with on-chip supply regulators with programmability and initialization. In one embodiment, an integrated circuit, includes: an initialization circuit to assert an initialization signal during powering up of the integrated circuit; a control ... | 04/29/2008 |
| 7365585 | Apparatus and method for charge pump slew rate control An apparatus and method for improving memory cell reliability is disclosed. The slew rate is reduced in an applied voltage signal used to program a memory cell when Fowler-Nordheim (FN) tunneling injection is detected. The applied programming signal is provided by a... | 04/29/2008 |
| 7366931 | Memory modules that receive clock information and are placed in a low power state Embodiments described herein provide a power saving state for a memory system. For example, a memory system may derive clocking information from a training pattern sent over a memory channel. A memory may comprise a link to receive training frames, and circuitry to ... | 04/29/2008 |
| 7362647 | Power control circuit A power control circuit for an integrated circuit module includes at least one switch device coupled between a supply voltage and a node of the integrated circuit module; and a switch control module having a first terminal coupled to the switch device and a second t... | 04/22/2008 |
| 7362646 | Semiconductor memory device A semiconductor memory device includes a memory cell array provided in a cell array area and including a plurality of memory cells, a source potential line which applies a source potential to the memory cells, a switching element group provided in the cell array are... | 04/22/2008 |
| 7362651 | Using common mode differential data signals of DDR2 SDRAM for control signal transmission A double-data-rate two synchronous dynamic random access (DDR2) memory circuit includes a low-speed input path and a high-speed input path coupled thereto by an input coupling and forming a common input, the common input coupled to a memory core, the memory core hav... | 04/22/2008 |
| 7362161 | Power supply switching circuit, data processing device, and method of controlling data processing device A power supply switching circuit includes a detection circuit which detects a reduction in a voltage level of the main power supply and outputs a detection signal; a first switch circuit which connects a main power supply to an internal power supply node before a re... | 04/22/2008 |
| 7362644 | Configurable MRAM and method of configuration A configurable MRAM device is achieved. The device comprises a memory array of magnetic memory cells. A first part of the array comprises the memory cells that can be accessed for reading and writing during normal operation. A second part of the array comprises the ... | 04/22/2008 |
| 7362641 | Method and system for low power refresh of dynamic random access memories A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memo... | 04/22/2008 |
| 7362631 | Semiconductor memory device capable of controlling drivability of overdriver A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for se... | 04/22/2008 |
| 7362652 | Semiconductor circuit A semiconductor circuit which includes one or plural fuse circuits being disconnectable and having a connected or disconnected state and a control circuit controlling a controlled circuit is provided. The control circuit controls the controlled circuit according to ... | 04/22/2008 |
| 7362084 | Fast voltage regulators for charge pumps A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast sta... | 04/22/2008 |
| 7360131 | Printer controller having tamper resistant shadow memory A printer controller is provided having an integrated circuit incorporating a processor and memory. The memory stores a set of data representing program code and/or an operating value for printer control. Each bit of the data is stored as a bit/inverse-bit pair in c... | 04/15/2008 |
| 7360107 | Method of controlling power within a disk array apparatus A power supply unit generates a predetermined voltage from power supplied from an external power supply and outputs the voltage to a power supply line. A battery charge/discharge circuit charges a battery with the voltage supplied and determines whether to supply an... | 04/15/2008 |
| 7359811 | Programmable logic device with power supply noise monitoring Programmable logic device power supply noise levels are characterized using internal measurements. By making power supply noise measurements internally, noise measurements are made without influence from device packaging or circuit board environmental effects. The i... | 04/15/2008 |
| 7360005 | Software programmable multiple function integrated circuit module An electrically programmable multiple selectable function integrated circuit module has a plurality of optionally selectable function circuits, which receive and manipulate a plurality of input data signals. The outputs of the plurality of optionally selectable func... | 04/15/2008 |
| 7359270 | Self refresh period signal generation device A self refresh period signal generating device includes an internal temperature sensor; an extended mode register set for storing a first temperature code which corresponds to temperature measured by an external temperature sensor; a selection means for selecting on... | 04/15/2008 |
| 7359272 | Circuit and method for an SRAM with reduced power consumption A circuit and method for providing an SRAM memory with reduced power consumption, the SRAM memory particularly useful for embedding SRAM memory with other logic and memory functions in an integrated circuit. A lower supply voltage is provided to the peripheral circu... | 04/15/2008 |
| 7358794 | Power supply circuit A power supply circuit includes a charge pump converting voltage and a regulator controlling the converting operation of the charge pump. The charge pump stops the converting operation after a first delay time from when an output of the charge pump goes over a refer... | 04/15/2008 |
| 7360023 | Method and system for reducing power consumption in a cache memory A method and system are for reducing power consumption in a multi-way set-associative cache memory. During a first clock cycle, in response to an address, an associated set is identified in the cache memory. The address is compared to respective tag portions of bloc... | 04/15/2008 |
| 7359277 | High speed power-gating technique for integrated circuit devices incorporating a sleep mode of operation A high speed power-gating technique for an integrated circuit device having a Sleep Mode of operation comprises providing an output stage coupled between a supply voltage source and a reference voltage source and driving a gate terminal of least one element of the o... | 04/15/2008 |
| 7360104 | Redundant voltage distribution system and method for a memory module having multiple external voltages A memory assembly module including an on-board voltage regulator for converting an externally supplied voltage into appropriate local voltage levels for powering memory devices of the memory assembly module. ... | 04/15/2008 |
| 7358764 | Preset and reset circuitry for programmable logic device memory elements Integrated circuits such as programmable logic device integrated circuits have arrays of memory elements into which configuration data is loaded. The memory elements are formed form a pair of independently-powered cross-coupled inverters. Control circuitry generates... | 04/15/2008 |
| 7355875 | Nonvolatile semiconductor memory device having capacitor arranged between power supplies to prevent voltage fluctuation A nonvolatile semiconductor memory device comprises, an internal memory cell array formed in internal area of a surface of semiconductor substrate, a row decoder and a column decoder formed in the internal area to select memory cell of the internal memory cell array... | 04/08/2008 |
| 7355915 | Memory circuit with supply voltage flexibility and supply voltage adapted performance The inventive memory circuit comprises a plurality of memory cells. The memory circuit further comprises a memory access means being controlled by at least one control signal. In addition, a control means for generating the at least one control signal is contained i... | 04/08/2008 |
| 7356718 | Semiconductor memory circuit and method for operating the same in a standby mode A semiconductor memory circuit having a controller by means of which the semiconductor memory circuit can be switched into a standby mode with a reduced power requirement, comprises an analog subcircuit having a power input and a signal output and is characterized b... | 04/08/2008 |
| 7355896 | System for improving endurance and data retention in memory devices A memory system includes a memory block having at least one memory cell. The current is sensed after the erase operations of the memory cell. A signal is generated in response to the current dropping below a predetermined level after the erase operations of the memo... | 04/08/2008 |
| 7355894 | Programming flash memories A flash memory device has an array of flash memory cells, a detector for detecting an external voltage applied to the flash memory device, and a command control circuit for controlling access to the array of flash memory cells. The command control circuit is adapted... | 04/08/2008 |
| 7352641 | Dynamic memory throttling for power and thermal limitations In one embodiment, a memory controller is coupled to a memory subsystem and controls accesses to the memory subsystem. In addition, a temperature sensor is positioned to detect a temperature associated with the memory subsystem. In this embodiment, the memory contro... | 04/01/2008 |
| 7352644 | Semiconductor memory with reset function A synchronous dynamic random access memory (SDRAM) integrated circuit (IC) configured to receive an external Reset signal for resetting the IC includes an input buffer configured to generate a buffered reset signal RST from the external Reset signal. The SDRAM IC fu... | 04/01/2008 |
| 7353490 | Power network synthesizer for an integrated circuit design A plan for a power network for an integrated circuit device is automatically preparing in two stages. In a first stage, a number of simplified plans are prepared on a global scale, without regard to design rule checking constraints and routing blockages. Next, the s... | 04/01/2008 |
| 7352208 | Integrated circuit having a plurality of output drivers One embodiment of the invention provides an integrated circuit having a plurality of output drivers for driving signals from the integrated circuit and having a plurality of supply terminals to apply a supply voltage to the integrated circuit, the plurality of outpu... | 04/01/2008 |
| 7352609 | Voltage controlled static random access memory A static random access memory (SRAM) (200, 400) comprising a plurality of SRAM cells (204), a plurality of wordlines (WL0-WLN) and a voltage regulator (240, 240′, 300, 516) for driving the wordlines with a wordline voltage signal (VWLP)... | 04/01/2008 |
