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| Number | Title | Issue Date |
| 7433257 | Semiconductor memory device When a memory cell is inactive, a memory cell power supply voltage control circuit decreases the power supply voltage supplied to the memory cell down to a memory cell holding voltage, thereby reducing the leak current flowing in the memory cell. By reducing the lea... | 10/07/2008 |
| 7430148 | Volatile memory elements with boosted output voltages for programmable logic device integrated circuits Integrated circuits are provided that have memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable logic including transistors with gates. When loaded with conf... | 09/30/2008 |
| 7430149 | Semiconductor device There is provided a semiconductor device supplied with internal power generated by an internal power generation circuit to perform a stable operation and, also, suppress power consumption. A control circuit, a row/column decoder and a sense amplifier are driven by a... | 09/30/2008 |
| 7430676 | Method and apparatus for changing the clock frequency of a memory system One embodiment of the present invention provides a system that facilitates changing a clock frequency in a memory system. During operation, the system receives a command to change the clock frequency to a new clock frequency. The system then iteratively changes the ... | 09/30/2008 |
| 7427031 | Semiconductor memory device A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer contro... | 09/23/2008 |
| 7428164 | Semiconductor memory device When threshold voltages of constituent transistors are reduced in order to operate an SRAM circuit at a low voltage, there is a problem in that a leakage current of the transistors is increased and, as a result, electric power consumption when the SRAM circuit is no... | 09/23/2008 |
| 7428176 | Charge pump for programmable semiconductor memory A depletion type active capacitor may transfer charge from an oscillator to an address line that needs to be boosted for programming. Such a charge pump may be useful in semiconductor memories such as flash memories, EEPROM memories, and NAND EEPROM memories. In som... | 09/23/2008 |
| 7428177 | Reference potential generating circuit and semiconductor memory device having the same A reference potential generating circuit has a current mirror amplifier (CM11) supplied with an input reference potential and a feedback level, an output transistor (QP11) supplied with an output of the current mirror amplifier as an input and producin... | 09/23/2008 |
| 7426147 | Power supply voltage control circuit A power supply voltage control circuit supplying a power supply voltage to a memory cell array, including word lines extending along row direction, bit lines extending along column direction, plate lines extending along the row direction, and a plurality of unit cel... | 09/16/2008 |
| 7426151 | Device and method for performing a partial array refresh operation An internal voltage generator includes a control section and a switchable internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The interna... | 09/16/2008 |
| 7426152 | Semiconductor memory device and semiconductor device A technology capable of improving the yield by the trimming of internal properties of a semiconductor device is provided. A semiconductor device is provided with an internal voltage step-down circuit and an internal voltage step-up circuit whose property values (int... | 09/16/2008 |
| 7423899 | SRAM device having forward body bias control A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inve... | 09/09/2008 |
| 7424629 | Data controlled power supply apparatus A power supply, and a method of controlling the power supply, in which more or less power capacity of the power supply is activated depending on the state of a digital data signal on a data bus. The power supply has a control circuit which detects the number of “z... | 09/09/2008 |
| 7420866 | Method and system of operating mode detection A system and method of providing a voltage to a non-volatile memory is disclosed. The system includes an output pin to provide an output voltage to a non-volatile memory. The system also includes a memory to store a table. The table includes a plurality of operating... | 09/02/2008 |
| 7420831 | Semiconductor chip and semiconductor chip package comprising semiconductor chip Embodiments of the invention provide a semiconductor chip and a semiconductor chip package comprising a semiconductor chip. In one embodiment, the invention provides a semiconductor chip comprising a memory cell array, a control circuit, and a chip selection signal ... | 09/02/2008 |
| 7420834 | Semiconductor integrated circuit device The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells ... | 09/02/2008 |
| 7417889 | Independent-gate controlled asymmetrical memory cell and memory using the cell Techniques are provided for employing independent gate control in asymmetrical memory cells. A memory circuit, such as an SRAM circuit, can include a number of bit line structures, a number of word line structures that intersect the bit line structures to form a num... | 08/26/2008 |
| 7417913 | Fuse cell having adjustable sensing margin An apparatus, a method, and a system for fuse cells are disclosed herein. In various embodiments, a fuse cell may include circuitry to adjust a sensing margin. A fuse cell may include first and second fuse cells, and first and second resistance devices. The first re... | 08/26/2008 |
| 7418612 | Semiconductor device with a power down mode The semiconductor device with the power down mode includes a power down detecting block for generating a power down mode signal by detecting if the power down mode is activated, a power source control block for producing a power control signal whose ratio of an enab... | 08/26/2008 |
| 7414890 | Semiconductor device including a high voltage generation circuit and method of a generating high voltage A semiconductor memory device comprises a first pump clock generator configured to generate a first pump clock signal based on a first power supply voltage. The device also comprises a first charge pump configured to generate a first pump output voltage in response ... | 08/19/2008 |
| 7414908 | Magnetic memory device A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding p... | 08/19/2008 |
| 7414912 | Semiconductor flash memory A semiconductor flash memory includes an erase/write control unit that, when performing an erase/write operation of read memory cells, reads and senses memory current of the read memory cells for each memory cell, and adjusts threshold voltage of each of the read me... | 08/19/2008 |
| 7411854 | System and method for controlling constant power dissipation A method for controlling the constant power dissipation of a memory cell includes initially measuring the resistance of the memory cell, and subsequently controlling a source to apply a variable level of current or voltage to the memory cell. The variable level of t... | 08/12/2008 |
| 7411847 | Burn in system and method for improved memory reliability The present invention relates to a system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The present invention includes writing a logic 0 into all the memory cells in a memory structure... | 08/12/2008 |
| 7411855 | Semiconductor device with improved power supply arrangement A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both ... | 08/12/2008 |
| 7411856 | Semiconductor device with improved power supply arrangement A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both ... | 08/12/2008 |
| 7411853 | Volatile memory elements with elevated power supply levels for programmable logic device integrated circuits Integrated circuits are provided that have volatile memory elements. The memory elements produce output signals. The integrated circuits may be programmable logic device integrated circuits containing programmable core logic including transistors with gates. The cor... | 08/12/2008 |
| 7411805 | Semiconductor integrated circuit device A clock-generating circuit for forming internal clock signals by comparing a signal obtained by delaying, through a variable delay circuit, an input clock signal input through an external terminal with the input clock signal through a phase comparator circuit, and s... | 08/12/2008 |
| 7408818 | Semiconductor device undergoing defect detection test A semiconductor device has a first operation mode and a second operation mode in which power supply with a higher voltage value than that in the first operation mode is provided. The semiconductor device includes a memory portion having memory cells for storing data... | 08/05/2008 |
| 7408817 | Voltage generating circuit, semiconductor memory device comprising the same, and voltage generating method A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output no... | 08/05/2008 |
| 7408829 | Methods and arrangements for enhancing power management systems in integrated circuits Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternat... | 08/05/2008 |
| 7408830 | Dynamic power supplies for semiconductor devices This invention discloses a power supply management circuit which comprises at least one switching circuit coupled between a power supply and a power recipient circuit, and at least one voltage booster circuit coupled between a control circuit and the power recipient... | 08/05/2008 |
| 7408831 | Semiconductor device including voltage level conversion output circuit A semiconductor device for easily changing an operating voltage of an I/O circuit. The I/O circuit includes a first I/O cell, which operates with a first high-potential power supply, and a second I/O cell, which operates with a second high-potential power supply. Th... | 08/05/2008 |
| 7403435 | Memory unit and semiconductor device A memory unit that is capable of operating in a desired operation condition with less power consumption, and a semiconductor device using the memory unit. The memory circuit comprises a cell array in which a plurality of memory cells is arranged, a driver circuit, a... | 07/22/2008 |
| 7403441 | Power management unit for a flash memory with single regulation of multiple charge pumps A power management unit for a non-volatile memory device is proposed. The power management unit includes means for providing a reference voltage, resistive means for deriving a reference current from the reference voltage, means for generating a plurality of operati... | 07/22/2008 |
| 7403412 | Integrated circuit chip with improved array stability A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs ... | 07/22/2008 |
| 7403420 | Flash memory device and associated recharge method A flash memory device comprises first and second mat structures connected to respective first and second high voltage lines, and a switch circuit connected between the first and second high voltage lines. The switch circuit supplies a program voltage from the first ... | 07/22/2008 |
| 7400544 | Actively driven Vfor input buffer noise immunity A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memo... | 07/15/2008 |
| 7397721 | Standby leakage current reduction circuit and semiconductor memory device comprising the standby leakage current reduction circuit Embodiments of the invention provide a standby leakage current reduction circuit and a semiconductor memory device comprising the standby leakage current reduction circuit. The invention provides a circuit adapted to reduce standby leakage current in a semiconductor... | 07/08/2008 |
| 7397693 | Semiconductor memory device with memory cells operated by boosted voltage A memory using an SRAM memory cell intended for low-voltage operation is designed to decrease the threshold value of MOS transistors constituting the memory cell without substantial decrease in the static noise margin, which is the operational margin of the memory c... | 07/08/2008 |
