Did You Know...
...that Thomas Edison's patent application on his phonograph was approved by the Patent Office in just seven weeks? In contrast, it took Gordon Gould, the inventor of the laser, 30 years to obtain his patent -- finally awarded in 1988!
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| Number | Title | Issue Date |
| 7327628 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7327615 | Electric potential switching circuit, flash memory with electric potential switching circuit, and method of switching electric potential An electric potential switching circuit has an electric potential control circuit, an output circuit, and a precharge circuit connected to the output circuit. The electric potential control circuit generates a reference electric potential associated with an operatio... | 02/05/2008 |
| 7327598 | High performance, low leakage SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode An SRAM device and a method of placing a portion of memory cells of an SRAM device in an active mode is provided. In one embodiment, the SRAM device includes a hierarchical grouping of memory cells of memory cells and biasing circuitry, coupled to the hierarchical g... | 02/05/2008 |
| 7327629 | Circuit and method for reading an antifuse An antifuse circuit and antifuse reading method for determining whether an antifuse is programmed or un-programmed. An antifuse circuit includes a sensing circuit having a sense node coupled to the antifuse that is configured to generate a reference current and comp... | 02/05/2008 |
| 7327631 | Semiconductor memory device and method of operating semiconductor memory device A semiconductor memory device may include an oscillator circuit for generating an oscillation signal that is varied based on mode of operation, and a word line enable circuit for generating a word line enable signal in response to the oscillation signal. The device ... | 02/05/2008 |
| 7327630 | Memory cell power switching circuit in semiconductor memory device and method for applying memory cell power voltage A power (voltage) switching circuit in a semiconductor memory device, capable of reducing leakage current in a standby mode of operation and shortening the wake-up time when a standby mode is switched to an operation mode. The power (voltage) switching circuit compr... | 02/05/2008 |
| 7324390 | Low voltage operation dram control circuits Circuits and methods are described for reducing leakage current and speeding access within dynamic random access memory circuit devices. A number of beneficial aspects are described. A circuit is described for an enhanced sense amplifier utilizing complementary drai... | 01/29/2008 |
| 7324369 | MRAM embedded smart power integrated circuits An integrated circuit device includes a magnetic random access memory (“MRAM”) architecture and a smart power integrated circuit architecture formed on the same substrate using the same fabrication process technology. The fabrication process technology is a modu... | 01/29/2008 |
| 7324380 | Method for trimming the temperature coefficient of a floating gate voltage reference A voltage reference circuit provides a reference voltage that can be precisely programmed. The threshold voltage of a first non-volatile memory (NVM) transistor is programmed while coupled in parallel with a second NVM transistor. During programming, one or more cap... | 01/29/2008 |
| 7321252 | Semiconductor integrated circuit In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main ... | 01/22/2008 |
| 7321506 | Multivibrator protected against current or voltage spikes The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch ce... | 01/22/2008 |
| 7321257 | Semiconductor device capable of detecting an open bonding wire using weak current An IC chip has a series regulator built therein. A battery voltage is applied to an input pin. An output of a transistor constituting the series regulator occurs at an output pin via an output pad. A feedback signal derived from an output voltage occurs at an end of... | 01/22/2008 |
| 7321523 | System for monitoring processing device utilization in a computer A monitoring system capable of monitoring utilization of a processing device in a computer. The monitoring system includes a power supply voltage for supplying a core voltage to the processing device, and a comparator for comparing a voltage proportional to the core... | 01/22/2008 |
| 7321504 | Static random access memory cell A static random access memory (SRAM) cell having an inverter and a tri-state inverter. An input of the inverter is coupled to an output of the tri-state inverter and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter h... | 01/22/2008 |
| 7319346 | Circuit and method for trimming integrated circuits A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current i... | 01/15/2008 |
| 7319361 | Internal voltage generation circuit of a semiconductor device An internal voltage generation circuit of a semiconductor device is disclosed. The internal voltage generation circuit comprises a reference voltage generator for generating a reference voltage having different levels depending on different operation modes of the se... | 01/15/2008 |
| 7319630 | Current-limited latch A current-limited latch circuit is used within a nonvolatile memory integrated circuit for decoding, programming, erase, and other operations. In one implementation, there are a number of latches connected together in parallel between two power supply lines. A curre... | 01/15/2008 |
| 7319609 | Non-volatile memory device with a programming current control scheme A non-volatile memory device includes at least one current source coupled to a bit line, along which at least two memory cells sharing a common source line are connected, for generating a programming current on the bit line when one of the memory cells is selected f... | 01/15/2008 |
| 7319612 | Performing multiple read operations via a single read command In one embodiment, the present invention includes a method for performing a plurality of read operations on a nonvolatile array of a memory according to a single read command, and storing data from the plurality of read operations in a volatile array of the memory. ... | 01/15/2008 |
| 7319626 | High voltage generating circuit and method and semiconductor memory device including the circuit A first pump circuit is coupled to a first pump signal line and is configured to generate a first voltage greater than a power supply voltage at an output thereof responsive to transition of the first pump signal line from a ground voltage to the power supply voltag... | 01/15/2008 |
| 7319633 | Semiconductor device A semiconductor device in which a current consumption when a word line being selected is suppressed and accurate data reading is carried out. The semiconductor device of a semiconductor device of the invention comprises a data storage means and a power source contro... | 01/15/2008 |
| 7317632 | Non-volatile memory storage device and controller therefor A non-volatile memory storage device with functions of boosting supply voltage and signal level can adopt a non-volatile memory having an operating voltage higher than the supply voltage provided by the host device as a storage medium. The non-volatile memory storag... | 01/08/2008 |
| 7317635 | User configurable commands for flash memory A memory device includes a plurality of memory dies, each having an assigned address. A register on each die is reset on power-up. Boot data is loaded as part of the initialization routine. If the boot data includes a reconfigured command, that command is loaded int... | 01/08/2008 |
| 7317642 | Overdrive period control device and overdrive period determining method An overdrive period control device includes a pre-charge circuit connected to a node on which a potential is detected and for raising a potential at the node to a first potential; a delay element one terminal of which is connected to the node; a charge circuit suppl... | 01/08/2008 |
| 7317328 | Test device for on die termination An on die termination (ODT) test device includes: a control unit for selectively activating a plurality of pull-up signals and a plurality of pull-down signals by performing a logic operation to an ODT control signal for controlling a resistor of a termination termi... | 01/08/2008 |
| 7317652 | Semiconductor device, nonvolatile semiconductor memory, system including a plurality of semiconductor devices or nonvolatile semiconductor memories, electric card including semiconductor device or nonvolatile semiconductor memory, and electric device with which this electric card can be used A semiconductor device of this invention includes a first circuit for initializing a predetermined circuit in accordance with the level of a power source voltage, a second circuit for controlling the output from the first circuit by activation or deactivation, and a... | 01/08/2008 |
| 7315483 | Circuit for selecting a power supply voltage and semiconductor device having the same A semiconductor memory device capable of reducing the number of pads is provided. The semiconductor memory device may include a pad, a power supply voltage generating circuit and a voltage selection circuit. The power supply voltage generating circuit may generate o... | 01/01/2008 |
| 7315194 | Booster circuit A booster circuit includes a first booster unit having a first output terminal from which a boosted voltage is output. The first output terminal is connected to an external output terminal. A second booster unit has a second output terminal from which a boosted volt... | 01/01/2008 |
| 7315481 | Semiconductor memory When it is judged that real bit lines connected to real memory cells are liable to be connected to adjacent circuit elements to be electrically short-circuited, dummy bit lines are connected to voltage lines which supply voltages to the circuit elements. For example... | 01/01/2008 |
| 7313044 | Integrated semiconductor memory with temperature-dependent voltage generation An integrated semiconductor memory device includes a temperature sensor circuit to generate a temperature-dependent control signal, a reference circuit to generate a temperature-independent reference signal, a comparator circuit and a voltage generator circuit. The ... | 12/25/2007 |
| 7313048 | Reset detection circuit in semiconductor integrated circuit A reset detection circuit for a logic circuit and a RAM includes a first determining circuit, a second determining circuit and a reset signal generating circuit. The first determining circuit operates with a first voltage and determines whether a second voltage is e... | 12/25/2007 |
| 7312109 | Methods for fabricating fuse programmable three dimensional integrated circuits A method of fabricating a field programmable integrated circuit comprised of: constructing a semiconductor device comprising a fuse circuit to customize the logic content of a programmable logic circuit; and attaching said semiconductor device in a detachable lid pa... | 12/25/2007 |
| 7313032 | SRAM voltage control for improved operational margins A static random access memory (“SRAM”) is provided which includes a plurality of SRAM cells arranged in an array. The array includes a plurality of rows and a plurality of columns. The SRAM includes a plurality of voltage control corresponding to respective ones... | 12/25/2007 |
| 7313018 | Methods and apparatus for a non-volatile memory device with reduced program disturb A non-volatile memory device includes a plurality of power control circuits interfaced via a single Y multiplexer with an array of memory cells. The multiple power control circuits provide multiple pre-charge paths configured to pre-charge the drain node of a target... | 12/25/2007 |
| 7312649 | Voltage booster power supply circuit A voltage booster power supply circuit using a first voltage VDD3 and a second voltage VDDM to boost the first voltage VDD3, which is higher than the second voltage, to provide a boosted voltage VPP. Thus, a high efficiency of generation of a boosted v... | 12/25/2007 |
| 7310277 | Non-volatile semiconductor storage device with specific command enable/disable control signal The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 1... | 12/18/2007 |
| 7310744 | Systems and methods for out-of-band booting of a computer The present invention is directed to systems and methods for remotely booting a server computer system. A boot request is received from the server computer. An access request is transmitted to a boot management system via a secondary communication channel in respons... | 12/18/2007 |
| 7310700 | Microcomputer, programming method and erasing method The present invention provides a microcomputer wherein in a system which needs to respond to events developed at intervals each shorter than an erase/program process time, erase/programming can be effected on an on-chip non-volatile memory as necessary during its pr... | 12/18/2007 |
| 7307907 | SRAM device and a method of operating the same to reduce leakage current during a sleep mode An SRAM device and a method of operating an SRAM device. In one embodiment, the SRAM device includes (1) an SRAM array coupled to row peripheral circuitry by a word line and coupled to column peripheral circuitry by bit lines and (2) a sleep mode voltage controller ... | 12/11/2007 |
| 7307904 | Semiconductor device The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The dat... | 12/11/2007 |
