Class 365/222 - Data refresh

Subclass of Class 365 - Static information storage and retrieval
Definition: Subject matter wherein decaying information is read before
No. of patents: 2597
Last issue date: 05/29/2012

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Number	Title	Issue Date
8189418	Refresh signal generating circuit A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable si...	05/29/2012
8184495	Semiconductor memory device for controlling operation of delay-locked loop circuit A semiconductor memory device for controlling an operation of a delay-locked loop (DLL) circuit includes a DLL circuit that receives an external clock signal and that performs a locking operation on the external clock signal and an internal clock signal, thereby obt...	05/22/2012
8174921	Semiconductor memory device having shared temperature control circuit A semiconductor memory device includes a plurality of memory banks; a plurality of temperature sensing circuits, and a shared control circuit. The temperature sensing circuits correspond to the memory banks and each is disposed in the vicinity of a corresponding mem...	05/08/2012
8169847	Semiconductor memory apparatus and refresh control method of the same A semiconductor memory apparatus and refresh control method are presented. The semiconductor memory apparatus includes a memory cell block composed of a multiplicity of floating body cell (FBC) transistors. Each FBC transistor has a gate connected to a word line, a ...	05/01/2012
8164967	Systems and methods for refreshing non-volatile memory Systems and methods are disclosed for managing a non-volatile memory (“NVM”), such as a flash memory. To prevent data errors due to leakage effects, the NVM may be refreshed. For example, a reserved portion of the NVM may be selected, and a predetermined pattern...	04/24/2012
8154940	Method of reducing current of memory in self-refreshing mode and related memory The present invention provides a method of reducing current of a memory in a self-refreshing mode and a related memory. The memory includes a word line driver and a controller, and the word line driver includes a transistor. The transistor has a control terminal, a ...	04/10/2012
8154939	Control method for nonvolatile memory and semiconductor device In a nonvolatile memory, the threshold is restored to a state before changing, without increasing number of writing undesirably. In a system including a nonvolatile memory, a random number generator, and a controller accessible to the nonvolatile memory, every time ...	04/10/2012
8149641	Active cycle control circuit for semiconductor memory apparatus An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during t...	04/03/2012
8144539	Semiconductor memory device for self refresh and memory system having the same A semiconductor memory device includes a memory core unit including a memory cell array including a plurality of memory cells and a sense amplifier to sense and amplify data of the plurality of memory cells, and a self refresh control unit to apply at least one firs...	03/27/2012
8139433	Memory device control for self-refresh mode To ensure that a memory device operates in self-refresh mode, the memory controller includes (1) a normal-mode output buffer for driving a clock enable signal CKE onto the memory device's CKE input and (2) a power island for driving a clock enable signal CKE_prime o...	03/20/2012
8130586	Semiconductor memory device and method of controlling the same An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circ...	03/06/2012
RE43223	Dynamic memory management In a method, system and apparatus for management of dynamic memory in battery-powered devices, information is stored in dynamic memory, such as SDRAM chips. Chip partitioning minimizes the number of chips requiring power, minimum refresh rates reduce the power neede...	03/06/2012
8130585	System and method for hidden-refresh rate modification A system and method for modifying a hidden-refresh rate for dynamic memory cells includes monitoring a control signal from a processor and performing a hidden-refresh of dynamic data at a first refresh rate when the control signal is asserted. The dynamic data is re...	03/06/2012
8116162	Dynamic signal calibration for a high speed memory controller Within an integrated circuit comprising a memory controller, a method can include, responsive to determining that the memory controller is performing a refresh operation, calculating a new tap setting according to a new maximum value and an old tap setting of the de...	02/14/2012
8116161	System and method for refreshing a DRAM device The present invention provides a system and method for refreshing a DRAM device without interrupting or inhibiting read and write operations of the DRAM device. The system may includes refresh control circuitry that selectively generates requests to perform refresh ...	02/14/2012
8111574	Circuit and method for controlling self-refresh cycle The present invention relates to a circuit and a method for controlling a self-refresh cycle of a dynamic random access memory or DRAM. A cell voltage is directly detected so that a self-refresh cycle can be variably controlled. Detectors each detecting whether or n...	02/07/2012
8111575	Semiconductor device There is provided a semiconductor device including: a temperature sensor detecting temperature; an inner circuit operating when supplied with a power supply voltage from a power supply line; a switch connected between the power supply line and the inner circuit; and...	02/07/2012
8107310	Semiconductor memory device and method for operating the same A semiconductor memory device includes a bank having a plurality of mats, an address counting unit configured to receive an auto-refresh command consecutively applied at predetermined intervals corresponding to a number of the mats, and sequentially count an interna...	01/31/2012
8098537	Data refresh for non-volatile storage Techniques are disclosed to refresh data in a non-volatile storage device often enough to combat erroneous or corrupted data bits, but not so often as to interfere with memory access or to cause excessive stress on the memory cells. One embodiment includes determini...	01/17/2012
8094512	Semiconductor memory device with individual and selective refresh of data storage banks A conventional semiconductor memory device may be in need of a special refresh sequence if it is desired to reduce the current consumption in connection with a refresh operation. With this in view, there is disclosed a semiconductor memory device 1 that has a...	01/10/2012
8081533	Semiconductor memory device A semiconductor memory device is provided between a refresh request circuit and a command decoder, and includes a refresh synchronous circuit for deactivating a refresh request if an external access request is output from the command decoder. The semiconductor memor...	12/20/2011
8077535	Memory refresh apparatus and method A system and method are provided. The system and method simulate a DRAM memory circuit using an interface circuit connected to a plurality of other DRAM memory circuits. In response to the receipt of a refresh control signal, a first refresh control signal is sent t...	12/13/2011
8077536	Method of operating semiconductor memory device with floating body transistor using silicon controlled rectifier principle A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conduct...	12/13/2011
8077537	Memory device, memory controller and memory system Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to ...	12/13/2011
8072829	Dynamic semiconductor memory with improved refresh mechanism Various embodiments for implementing refresh mechanisms in dynamic semiconductor memories that allow simultaneous read/write and refresh operations. In one embodiment, the invention provides a synchronous multi-bank dynamic memory circuit that employs a flag to indi...	12/06/2011
RE42976	Semiconductor memory device with reduced data access time A memory device includes at least two cell blocks connected to a global bit line for outputting data in response to an instruction; at least one global bit line connection unit for selectively connecting the global bit line to each cell block under control of a cont...	11/29/2011
8068375	Semiconductor device and method of refreshing the same A semiconductor device according to the present invention has an address scrambling circuit for performing address scrambling operation of an address and a redundancy judging circuit for judging that redundancy judgment is performed about the address scrambled by th...	11/29/2011
8054707	Low energy memory component The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply volta...	11/08/2011
8050128	Refresh signal generating circuit A refresh signal generating circuit of a semiconductor memory device includes a flag signal generator which generates a flag signal in response to a refresh signal and a precharge signal, a clock enable signal buffer which generates first and second buffer enable si...	11/01/2011
8045413	High speed DRAM architecture with uniform access latency A Dynamic Random Access Memory (DRAM) performs read, write, and refresh operations. The DRAM includes a plurality of sub-arrays, each having a plurality of memory cells, each of which is coupled with a complementary bit line pair and a word line. The DRAM further in...	10/25/2011
8036060	Semiconductor device in which a memory array is refreshed based on an address signal In an SDRAM of reduced current consumption, a signal RAS for performing refresh while temporally splitting refresh becomes active N times (where N is an integer and Nε2 holds) in a single refresh time period (indicated by a signal REF) to thereby refresh an interna...	10/11/2011
8027216	Semiconductor memory device A memory may includes: word lines; bit lines; memory array blocks including memory cells, each memory array block being a unit of a data read operation or a data write operation; a row decoder configured to selectively drive the word lines; sense amplifiers configur...	09/27/2011
8023353	Semiconductor memory device, refresh control method thereof, and test method thereof The present invention provides a semiconductor memory device which reduces current consumption in a standby state owing to a suitable refresh-thinning-out function, and a refresh control method thereof. When the refresh-thinning-out function is added while a refresh...	09/20/2011
8014222	Control of inputs to a memory device A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the ...	09/06/2011
8009497	Auto-refresh control circuit and a semiconductor memory device using the same An auto-refresh control circuit includes a control signal generating section configured to simultaneously or individually enable first and second control signals in response to an information combination signal having refresh information and operation mode informati...	08/30/2011
8009498	Memory refresh system and operating method thereof A memory refresh system includes a comparative detection circuit, a logic circuit, and a timing circuit. The comparative detection circuit detects a voltage of the storage capacitor of a memory cell of the memory and generates a corresponding digital code by compari...	08/30/2011
8004920	Power saving memory apparatus, systems, and methods Some embodiments include a voltage generator to generate a voltage to apply to a line used to access a memory cell of a memory device in which the voltage is applied to the line when the memory cell is not being accessed, and a power controller to cause the voltage ...	08/23/2011
8004921	Memory device, memory controller and memory system Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to ...	08/23/2011
8000164	Self refresh operation of semiconductor memory device A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self ...	08/16/2011
8000163	Self refresh operation of semiconductor memory device A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self ...	08/16/2011

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Class 365/222 - Data refresh