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...that Kleenex tissue was originally designed to be a gas mask filter? It was developed at the beginning of World War I to replace cotton, which was then in short supply as a surgical dressing.
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| Number | Title | Issue Date |
| 8094511 | Non-volatile memory device having high speed serial interface A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals re... | 01/10/2012 |
| 8036059 | Semiconductor memory circuit, circuit arrangement and method for reading out data A circuit arrangement for reading out data time delayed from a semiconductor memory comprises a common data input at which read data, which are read out of a semiconductor memory, are present and a data buffer FIFO for buffering the read data. The buffer FIFI compri... | 10/11/2011 |
| 7978557 | Semiconductor memory device and data processing system including the semiconductor memory device A semiconductor device that includes a plurality of memory cell arrays, a plurality of ports, a plurality of internal address generating circuits, and a controller. The plurality of internal address generating circuits may generate first and second internal addresse... | 07/12/2011 |
| 7948821 | Reduced signal interface memory device, system, and method A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one. ... | 05/24/2011 |
| 7826294 | Memory with output control An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control inpu... | 11/02/2010 |
| 7808855 | Distributed front-end FIFO for source-synchronous interfaces with non-continuous clocks In one embodiment, an integrated circuit such as an FPGA includes one or more data I/O blocks, one or more FIFOs, and a FIFO controller. At least one data I/O block receives an incoming bit stream from an external device. At least one FIFO is connected to receive a ... | 10/05/2010 |
| 7724598 | Megafunction block and interface A megafunction block is provided that includes a serial interface enabling a user to specify settings of a configurable block of a programmable logic device. The megafunction block includes a register array having the capability of translating address information in... | 05/25/2010 |
| 7660177 | Non-volatile memory device having high speed serial interface A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals re... | 02/09/2010 |
| 7660178 | Area efficient first-in first-out circuit A FIFO memory having an available capacity of no more than N words deep by M bits wide. A write port receives data to store in the FIFO memory, and a read port provides the data stored in the FIFO memory. X memories store the data, where each of the X memories has a... | 02/09/2010 |
| 7573770 | Distributed front-end FIFO for source-synchronized interfaces with non-continuous clocks In one embodiment of the invention, an integrated circuit, such as an FPGA, comprises a distributed FIFO architecture that supports data transfer from an external device, such as an SDRAM, via an interface that receives a non-continuous, asynchronous strobe clock an... | 08/11/2009 |
| 7570534 | Enqueue event first-in, first-out buffer (FIFO) In one embodiment, an apparatus comprises a queue, write control logic coupled to the queue and operable in a write clock domain, and a first-in, first-out buffer (FIFO) coupled to the write control logic. The queue is configured to store a plurality of data items, ... | 08/04/2009 |
| 7542365 | Apparatus and method for accessing a synchronous serial memory having unknown address bit field size An apparatus and method are provided for accessing a serial memory without knowing the required number of address bits. The apparatus comprises a pull circuit, a data out control circuit and a transition detector. The pull circuit causes the input terminal to be set... | 06/02/2009 |
| 7443762 | Synchronization circuit for a write operation on a semiconductor memory A synchronization circuit for handling and synchronizing a write operation on a semiconductor memory, in which a write operation contains a plurality of write commands, comprises a controllable first FIFO and a controllable second FIFO. The first FIFIO is clocked by... | 10/28/2008 |
| 7440351 | Wide window clock scheme for loading output FIFO registers A circuit provides the widest possible window for capturing data and preventing run-through in a FIFO register. The FIFO register includes two registers per I/O. Two FIFO input clocks are used, one for each FIFO register. When one FIFO clock is active, the other is ... | 10/21/2008 |
| 7436726 | Circuit for and method of reading data in an asynchronous FIFO including a backup address circuit for re-reading data A circuit for enabling reading data in an asynchronous FIFO memory of an integrated circuit is described. The circuit comprises a memory storing data in a plurality of slots having a corresponding plurality of addresses. A write address counter stores a write addres... | 10/14/2008 |
| 7436725 | Data generator having stable duration from trigger arrival to data output start A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing ... | 10/14/2008 |
| 7420869 | Memory device, use thereof and method for synchronizing a data word The invention includes a memory device with a register device to which an output of a multiplexer is connected. The input of the multiplexer is connected to a buffer store. In addition, the memory device includes a synchronization circuit having a control output con... | 09/02/2008 |
| 7397684 | Semiconductor memory array with serial control/address bus A semiconductor memory array for operation in a data storage system with at least one semiconductor memory chip for the storage of user data and one memory controller for control of the at least one semiconductor memory chip includes at least one unidirectional, ser... | 07/08/2008 |
| 7397727 | Write burst stop function in low power DDR sDRAM A write burst stop command function is provided for a semiconductor memory device, and in particular for a memory device having a write latency, such as is common in a low power double data rate (DDR) dynamic random access memory (DRAM) device. In the memory device,... | 07/08/2008 |
| 7397717 | Serial peripheral interface memory device with an accelerated parallel mode A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output term... | 07/08/2008 |
| 7394710 | Auto-recovery fault tolerant memory synchronization Automatic fault recovery of upsets in a memory controller are provided to minimize data loss. In addition to memory control, the present invention allows for the incorporation of majority voting circuits with integrated alignment between three voted data streams. Th... | 07/01/2008 |
| 7394715 | Memory system comprising memories with different capacities and storing and reading method thereof A memory system includes a first memory, a second memory, a determining unit, and an accessing unit. The capacity of the second memory is different from the capacity of the first memory. The first and the second memories are virtually partitioned into a first sectio... | 07/01/2008 |
| 7382637 | Block-writable content addressable memory device A content addressable memory device including a memory to store a searchable database, a search circuit, and a first-in-first-out storage circuit. The search circuit generates a plurality of address values that correspond to unoccupied storage locations within the m... | 06/03/2008 |
| 7379383 | Methods of DDR receiver read re-synchronization A method for reading data is provided. The method includes generating two or more pulses from a first clock signal by which the data to be read is received, using each generated pulse to latch data received at a corresponding time, and detecting a first time region ... | 05/27/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
| 7376041 | Semiconductor memory device and data read and write method of the same A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read contro... | 05/20/2008 |
| 7372755 | On-chip storage memory for storing variable data bits An improved on-chip storage memory and method for storing variable data bits, the memory including an on-chip storage memory system for storing variable data bits that has a memory for storing data bits, a wrapper for converting the memory into a first-in first-out ... | 05/13/2008 |
| 7371626 | Method for maintaining topographical uniformity of a semiconductor memory array A semiconductor device includes a memory array having a plurality of non-volatile memory cells. Each non-volatile memory cell of the plurality of non-volatile memory cells has a gate stack. The gate stack includes a control gate and a discrete charge storage layer s... | 05/13/2008 |
| 7373452 | Controller for controlling nonvolatile memory A memory controller is provided which is connected to a nonvolatile memory (e.g., a NAND flash memory) and a volatile memory (e.g., a DRAM or SDRAM), where the memory controller controls an access to the nonvolatile memory and the volatile memory in response to a me... | 05/13/2008 |
| 7372768 | Memory with address management The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of... | 05/13/2008 |
| 7368939 | Data input/output circuit included in semiconductor memory device A control circuit receives an external control signal in synchronism with an internal clock and generates an address signal and internal control signals. A data multiplexer has a plurality of input parallel lines and a plurality of output parallel lines and is switc... | 05/06/2008 |
| 7366006 | SRAM with read assist A Static Random Access Memory (SRAM) matrix with a read assist is described. The read assist reduces the probability associated with an SRAM matrix becoming upset by a radiation event. Each SRAM cell within the SRAM matrix includes an active delay for increasing Sin... | 04/29/2008 |
| 7366920 | System and method for selective memory module power management A memory module includes a memory hub that monitors utilization of the memory module and directs devices of the memory module to a reduced power state when the module is not being used at a desired level. System utilization of the memory module is monitored by track... | 04/29/2008 |
| 7366829 | TLB tag parity checking without CAM read An apparatus and method for expediting parity checked TLB access operations is described in connection with a multithreaded multiprocessor chip. This parity checking mechanism eliminates the need to read a CAM entry from a TLB during a TLB access by storing the tag ... | 04/29/2008 |
| 7366042 | Defective column(s) in a memory device/card is/are skipped while serial data programming is performed A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor... | 04/29/2008 |
| 7366823 | Method and system for memory access Described herein are a method and system for memory access. As the complexity of digital signal processing applications increases, designs may require multiple memory chips. To optimize the bandwidth of the data being accessed from the memory chips, blocks of data a... | 04/29/2008 |
| 7362619 | Data strobe synchronization circuit and method for double data rate, multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates... | 04/22/2008 |
| 7355917 | Two-dimensional data memory A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjac... | 04/08/2008 |
| 7355878 | Programmable logic devices optionally convertible to one time programmable devices Programmable logic devices (PLDs) that can be repeatedly erased and reprogrammed, e.g., during the testing and/or design phases, and then converted to one-time programmable (OTP) devices on a permanent basis, and methods of converting a PLD to an OTP device. In some... | 04/08/2008 |
| 7352648 | Semiconductor memory At least one complete cell array having a predetermined memory capacity and an incomplete cell array having a capacity smaller than the predetermined memory capacity are arranged in one direction. The incomplete cell array is disposed closer to a signal control unit... | 04/01/2008 |
