Did You Know...
...that after Parker Brothers executives turned down the game of Monopoly because it had "52 fundamental errors" (including taking too long to play), a copy of the game wound up in the home of the company president who stayed up until 1 a.m. to finish playing it? He was so impressed by the game that the next day he wrote to inventor Charles Darrow and offered to buy it!
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| Number | Title | Issue Date |
| 7894288 | Parallel data storage system A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received fr... | 02/22/2011 |
| 7800971 | Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat. ... | 09/21/2010 |
| 7760571 | Image memory architecture for achieving high speed access An image memory is composed of a memory cell array, first and second area selecting circuits, and a write circuit. The memory cell array includes memory elements arrayed in rows and columns, each of the memory elements being adapted to store pixel data. The first ar... | 07/20/2010 |
| 7626880 | Memory device having a read pipeline and a delay locked loop A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver ... | 12/01/2009 |
| 7619941 | Parallel data storage system A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received fr... | 11/17/2009 |
| 7593279 | Concurrent status register read Status information comprising data not stored in a memory array is efficiently read from a plurality of parallel memory devices sharing an N-bit data bus by configuring each memory device to drive the status information on a different subset M of the N bits, and tri... | 09/22/2009 |
| 7450457 | Memory system comprising a controller managing independent data transfer between input-output terminal, synchronous dynamic random access memory, and flash memory A memory system contributes to improvement in efficiency of a data process accompanying a memory access. The memory system has a rewritable nonvolatile memory, a buffer memory, and a controller. The controller controls, in response to an access request from an exter... | 11/11/2008 |
| 7447095 | Multi-port memory device A multi-port memory device having a plurality of ports performing a serial input/output (I/O) communication with external devices, and a plurality of banks performing a parallel I/O communication with the ports through a plurality of global I/O lines. The multi-port... | 11/04/2008 |
| 7447094 | Method for power-saving multi-pass sensing in non-volatile memory Power-saving techniques are employed in sensing a group of non-volatile memory cells in parallel. One technique is that the coupling of the memory cells to their bit lines is delayed during a precharge operation in order to reduce the cells'currents working against ... | 11/04/2008 |
| 7436725 | Data generator having stable duration from trigger arrival to data output start A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing ... | 10/14/2008 |
| 7397717 | Serial peripheral interface memory device with an accelerated parallel mode A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output term... | 07/08/2008 |
| 7394719 | Flash memory device with burst read mode of operation A flash memory device that includes a number of columns each of which is connected with a plurality of memory cells. A column selector circuit selects a part of the columns in response to a column address, and a plurality of sense amplifier groups are connected with... | 07/01/2008 |
| 7376034 | Parallel data storage system A parallel data storage system for storing data received from, or retrieving data to, a host system using multiple data storage devices. The system includes an interface for communicating with the host system and a buffer configured to store data sectors received fr... | 05/20/2008 |
| 7376021 | Data output circuit and method in DDR synchronous semiconductor device Embodiments of the present invention include a data output circuit that can read data in parallel from a plurality of latches in a pipeline circuit. Even-numbered data and odd-numbered data are simultaneously output over a single clock cycle, and are then converted ... | 05/20/2008 |
| 7355917 | Two-dimensional data memory A two-dimensional data memory (1) comprising memory elements which are arranged in rows and columns, which are designed to store in each case one data word, which in the row direction and in the column direction are coupled locally to their respectively adjac... | 04/08/2008 |
| 7349256 | Flash memory devices and methods of programming the same by overlapping programming operations for multiple mats A flash memory device is programmed by loading first data into a page buffer of a first mat. Second data is loaded into a page buffer of a second mat while programming the first data in a first memory block of the first mat. ... | 03/25/2008 |
| 7342835 | Memory device with pre-fetch circuit and pre-fetch method A memory device includes plural memory blocks, each memory block having memory cells arranged in wordlines and bitlines and a selector to select a wordline of memory cells. A group of first sense amplifiers are coupled to each memory block to at least one of read da... | 03/11/2008 |
| 7333909 | Method of and circuit for verifying a data transfer protocol A method of verifying a circuit implementing a data transfer protocol is disclosed. According to one embodiment of the invention, the method comprises steps of providing a block under test that implements a variable latency data transfer protocol; coupling a verific... | 02/19/2008 |
| 7333516 | Interface for synchronous data transfer between domains clocked at different frequencies The present invention provides an interface and method for synchronous data transfer between domains clocked at different frequencies. The interface includes a first latch for receiving data from a first domain clocked at one frequency when the first latch is select... | 02/19/2008 |
| 7313035 | Methods and apparatus for improved memory access A memory access scheme employing one or more sets of shift registers interconnected in series to which data may be loaded from or written into one or more memory devices. That is, data from the memory devices may be parallel loaded into the sets of shift registers a... | 12/25/2007 |
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to... | 12/18/2007 |
| 7307912 | Variable data width memory systems and methods Systems and methods disclosed herein provide for variable data width memory. For example, in accordance with an embodiment of the present invention, a technique for doubling a width of a memory is disclosed, without having to increase a width of the internal data pa... | 12/11/2007 |
| 7304909 | Control unit for deactivating and activating the control signals A control unit is set up to generate and output periodic clock signals, that are in sync with and at the same frequency as a periodic basic clock that is input into it, and periodic control signals, that are likewise in sync with the basic clock, and to turn on/turn... | 12/04/2007 |
| 7304887 | Method and apparatus for multi-plane MRAM A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of... | 12/04/2007 |
| 7304897 | Method and system for reading data from a memory Methods and systems consistent with this invention comprise a control circuit for reading data from a memory comprising a plurality of data channels. Such control circuits comprise at least one multiplexer, wherein the at least one multiplexer is configured to route... | 12/04/2007 |
| 7302505 | Receiver multi-protocol interface and applications thereof A receiver multi-protocol interface includes a wide bandwidth amplifier, a data sampling module, and a clocking module. The wide bandwidth amplifier amplifies a first formatted input signal or a second formatted input signal to produce an amplified input signal. The... | 11/27/2007 |
| 7289372 | Dual-port memory array using shared write drivers and read sense amplifiers Dual port memory blocks that have a reduced layout area are provided. The write drivers and sense amplifiers are shared between the dual ports to reduce the number of write drivers and sense amplifiers to save layout area. The write drivers for the two ports are use... | 10/30/2007 |
| 7286415 | Semiconductor memory devices having a dual port mode and methods of operating the same A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data received through a data bus to the first port in response to a leading edge... | 10/23/2007 |
| 7280417 | System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the... | 10/09/2007 |
| 7280400 | Reducing sneak currents in virtual ground memory arrays In a virtual ground memory array, sneak currents between input/output groups of sensed cells may be reduced by providing at least one column of programmed cells between the input/output groups. The sneak currents may arise when cells in each of two adjacent I/O grou... | 10/09/2007 |
| 7272064 | Thin film magnetic memory device for writing data of a plurality of bits in parallel For writing K-bit write data in parallel (K is integer at least 2), bit lines each arranged for each memory cell columns and at least K current return lines are provided. K selected bit lines to write the K-bit write data are connected in series in a single current ... | 09/18/2007 |
| 7272060 | Method, system, and circuit for performing a memory related operation A method, system, and circuit for performing a memory related operation are disclosed. An operating voltage is applied to a bitline and a neighboring bitline is precharged. The precharge voltage has a magnitude less than the operating voltage. Both voltages ramp up ... | 09/18/2007 |
| 7263018 | Compensating a long read time of a memory device in data comparison and write operations A memory device is disclosed that has a longer read time than write time and implements a parallel-read operation. The parallel-read operation saves reading time and thus accelerates a write operation that comprises a step of comparing incoming data with memory data... | 08/28/2007 |
| 7259702 | Memory device The present invention provides a memory device including a serial-parallel conversion section that converts serial data into parallel data, a parallel-serial conversion section that converts parallel data into serial data, and a parallel-parallel conversion section ... | 08/21/2007 |
| 7257020 | Thin film magnetic memory device having redundant configuration Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory celf columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory... | 08/14/2007 |
| 7233541 | Storage device The present invention is intended to significantly enhance processing efficiency. The card-type semiconductor storage device has a first data communication line group for connecting nonvolatile memories in a first port to a controller block and a second data communi... | 06/19/2007 |
| 7206913 | High speed memory system A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memor... | 04/17/2007 |
| 7200067 | Pad arrangement in semiconductor memory device and method of driving semiconductor device A semiconductor memory device comprising control pads and input/output I/O pads capable of reducing the data path for reading and writing data in a cell array, and a method for driving the semiconductor memory device are included. The semiconductor memory device com... | 04/03/2007 |
| 7196962 | Packet addressing programmable dual port memory devices and related methods In a packet addressing method, one or more memory blocks are selected from a plurality of memory blocks and one or more data I/O pads are selected from a plurality of data I/O pads via which data input or output to/from the selected memory blocks are loaded, memory ... | 03/27/2007 |
| 7187572 | Early read after write operation memory device, system and method A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment. The memory device includes an interface for providing a first write address, a first write data, and a read address. A ... | 03/06/2007 |
