Quotables
"The Americans have need of the telephone, but we do not. We have plenty of messenger boys."
Sir William Preece, chief engineer, British Post Office ; 1878
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8159893 | Data flow control in multiple independent port A system includes a memory controller and a plurality of memory devices connected in-series that communicate with the memory controller. Each of the memory devices has multiple independent serial ports for receiving and transmitting data. The memory controller a dev... | 04/17/2012 |
| 8045412 | Multi-stage parallel data transfer Apparatus and associated method for transferring data to memory, such as resistive sense memory (RSM). In accordance with some embodiments, input data comprising a sequence of logical states are transferred to a block of memory by concurrently writing a first logica... | 10/25/2011 |
| 8000162 | Voltage-controlled oscillator, phase-locked loop, and memory device A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in respon... | 08/16/2011 |
| 7944767 | Semiconductor device and data processing system Control information needed for executing data transmission/reception through a data terminal is received via its own control terminal in a first operation mode, and the control information is received by using the own control terminal and also a control terminal of ... | 05/17/2011 |
| 7843743 | Data output circuit for semiconductor memory apparatus A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit... | 11/30/2010 |
| 7751269 | Coupling device for transmitting data Embodiments of the invention relate generally to a coupling device, to a processor arrangement, to a data processing arrangement, and to methods for transmitting data. In an embodiment of the invention, a coupling device for coupling a memory, which has a serial dat... | 07/06/2010 |
| 7649795 | Memory with flexible serial interfaces and method for accessing memory thereof A memory system with a flexible serial interface and a memory accessing method thereof are provided. The memory system includes at least one of memories and a memory controller. The memory controller flexibly sets up serial link connection with each of the memories ... | 01/19/2010 |
| 7596046 | Data conversion circuit, and semiconductor memory apparatus using the same A data conversion circuit for a semiconductor memory apparatus includes a data conversion unit that has a plurality of latches for storing input data and outputting stored data as output data in response to a clock, and an operation mode selection unit that selects ... | 09/29/2009 |
| 7567476 | Semiconductor memory device and testing method thereof A semiconductor memory device includes mini arrays and a serial-parallel conversion circuit. The serial-parallel conversion circuit simultaneously writes two continuous data into mutually different mini arrays out of plural data that are continuously input synchrono... | 07/28/2009 |
| 7436725 | Data generator having stable duration from trigger arrival to data output start A data generator has stable duration from trigger arrival to substantial data output start. A memory provides parallel data according to a divided clock. An address counter provides the same address to the memory until a trigger signal arrives and starts increasing ... | 10/14/2008 |
| 7426144 | Semiconductor storage device A semiconductor storage device comprising: a transfer control circuit for prefetching data of a predetermined number of bits stored in a memory array in response to a read command, and transferring L bits of the prefetched data in parallel to an internal bus in sync... | 09/16/2008 |
| 7420865 | Pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same A pipe latch circuit for increasing data output speed, a semiconductor memory device with the pipe latch circuit and data output operation method of the same. The pipe latch circuit includes a selection signal generator and a pipe latch unit. The selection signal ge... | 09/02/2008 |
| 7397717 | Serial peripheral interface memory device with an accelerated parallel mode A serial peripheral flash memory device uses a plurality of dummy input/output terminals to enable the selection of a parallel mode for devices that have a slower serial clock speed. In parallel mode, data is transmitted over the plurality of dummy input/output term... | 07/08/2008 |
| 7385844 | Semiconductor device and method of controlling the same A semiconductor device includes: a memory cell array that has a plurality of non-volatile memory cells each having a first bit and a second bit in different regions in a charge storing layer; an SRAM array (first memory unit) that stores data to be written into the ... | 06/10/2008 |
| 7376041 | Semiconductor memory device and data read and write method of the same A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read contro... | 05/20/2008 |
| 7366042 | Defective column(s) in a memory device/card is/are skipped while serial data programming is performed A semiconductor device includes an interface which executes an interfacing process with a semiconductor memory, and a circuit which performs control to write serial data to the semiconductor memory while skipping a position of a defective column on the semiconductor... | 04/29/2008 |
| 7349289 | Two-bit per I/O line write data bus for DDR1 and DDR2 operating modes in a DRAM A data bus circuit for an integrated circuit memory includes a 4-bit bus per I/O pad that is used to connect the memory with an I/O block, but only two bits per I/O are utilized for writing. Four bits per I/O pad are used for reading. At every falling edge of an inp... | 03/25/2008 |
| 7350093 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 03/25/2008 |
| 7350018 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the ... | 03/25/2008 |
| 7342565 | Display device and a driver circuit thereof To provide a driver circuit that is simple and possessing a small surface area. The driver circuit comprises a shift register circuit and a plurality of latch circuits. The shift register circuit is composed of a plurality of register circuits having a clocked inver... | 03/11/2008 |
| 7340668 | Low power cost-effective ECC memory system and method A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words writte... | 03/04/2008 |
| 7336554 | Semiconductor memory device having a reduced number of pins A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted... | 02/26/2008 |
| 7333381 | Circuitry and methods for efficient FIFO memory Circuitry and methods for an efficient FIFO memory are provided. This efficient FIFO memory has two smaller standard single-port memory banks instead of one large dual-port memory bank, as in typical FIFO memories. Whereas the dual-port memory based FIFO memory can ... | 02/19/2008 |
| 7334078 | Method and system for handling streaming information One aspect of the present invention leads to a method of handling streaming information. The method includes receiving the streaming information and analyzing the streaming information to locate one or more points of interest in the streaming information. An index o... | 02/19/2008 |
| 7330382 | Programmable DQS preamble A method and apparatus for programming a data strobe (DQS) preamble in a memory by loading a defined set of bits into one or more registers of the memory, where one or more bits are formatted specifically for enabling the data strobe preamble. At least one of the bi... | 02/12/2008 |
| 7321961 | Method and apparatus to avoid collisions between row activate and column read or column write commands A method and apparatus to avoid collisions between row activate and column read or column write commands is presented. A memory controller includes control logic, activate allowed logic, and last column counter logic. The control logic sends particular values to the... | 01/22/2008 |
| 7319616 | Negatively biasing deselected memory cells In one embodiment, the present invention includes a method to supply a negative voltage to at least one deselected wordline of a memory array. Further, while the negative voltage is supplied to deselected wordlines, a positive voltage may be supplied to a selected w... | 01/15/2008 |
| 7315471 | Semiconductor memory device for storing multivalued data Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a sec... | 01/01/2008 |
| 7313639 | Memory system and device with serialized data transfer A memory system with serialized data transfer. The memory system includes within a memory controller and a plurality of memory devices. The memory controller receives a plurality of write data values from a host and outputs the write data values as respective serial... | 12/25/2007 |
| 7310756 | JTAG state machines with respective enable input and select input A TAP linking module (21, 51) permits plural TAPs (TAPs 1-4) to be controlled and accessed from a test bus (13) via a single TAP interface (20). ... | 12/18/2007 |
| 7310276 | Memory device and method having data path with multiple prefetch I/O configurations A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to... | 12/18/2007 |
| 7287143 | Synchronous memory device having advanced data align circuit A semiconductor device for performing an N-bit prefetch operation, N being a positive integer includes a data strobe buffering means for generating N number of align control signals based on a data strobe signal and a external clock signal; a receiving block in resp... | 10/23/2007 |
| 7280061 | Digital-to-analog converter using a frequency hopping clock generator Method and device for reducing the signal images at the output of a digital/analog converter. In a method for reducing the signal images at the output of a digital/analog converter, a frequency hopping clock generator provides a digital data signal whose data rate i... | 10/09/2007 |
| 7280386 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/09/2007 |
| 7280417 | System and method for capturing data signals using a data strobe signal A signal capture system and method is used to capture a data signal using a data strobe signal having a preamble of strobe signal transitions. The system includes a data latch circuit receiving the data signal. The data latch circuit is clocked by transitions of the... | 10/09/2007 |
| 7277345 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 10/02/2007 |
| 7277356 | Methods of controlling memory modules that support selective mode register set commands A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrat... | 10/02/2007 |
| 7278045 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 10/02/2007 |
| 7275172 | Apparatus and method for generating a delayed clock signal An apparatus and method for generating a delayed clock signal is provided. The clock signal generator includes a synchronizing circuit for generating an output clock signal from an input clock signal and further includes a delay circuit having an input coupled to th... | 09/25/2007 |
| 7272066 | Method and system for controlling refresh to avoid memory cell data losses A DRAM includes a register storing subsets of row addresses corresponding to rows containing at least one memory cell that is unable to store a data bit during a normal refresh cycle. Each subset includes all but the most significant bit of a corresponding row addre... | 09/18/2007 |
