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| Number | Title | Issue Date |
| 6335899 | Compensation capacitance for minimizing bit line coupling in multiport memory A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capa... | 01/01/2002 |
| 6333866 | Semiconductor device array having dense memory cell array and heirarchical bit line scheme A semiconductor device architecture (200) is disclosed. Like unit circuits (202), arranged in rows and columns, are coupled to lower conductive segments (204a-204h). The lower conductive segments (204a-204h) are arranged in an "open" configuration, allowi... | 12/25/2001 |
| 6317365 | Semiconductor memory cell A semiconductor memory cell is configured using a sense amplifier and a memory cell containing MOS transistors. In a write cycle, the sense amplifier inputs write data to accumulate charges in the memory cell. In a read cycle, the sense amplifier outputs ... | 11/13/2001 |
| 6240006 | Semiconductor memory device having reduced interconnection resistance Main word lines are shifted in the width direction in a memory array to generate an empty region formed by a shift-aside region. The width of a conductive interconnection line transmitting a desired signal/voltage is increased in this region. Accordingly,... | 05/29/2001 |
| 6212091 | Semiconductor memory device having a shielding line A semiconductor memory device has data bus lines which are connected to a memory cell array, and column selection lines, each of which is used to select a column of the memory cell array. The semiconductor memory device includes a shielding line placed be... | 04/03/2001 |
| 6205075 | Semiconductor memory device capable of reducing the effect of crosstalk noise between main bit lines and virtual main grounding lines This semiconductor memory device is provided with a plurality of main bit lines; a main bit line controller for controlling whether to impress a specific voltage on the main bit lines, connect the main bit lines to a sense amplifier, or place the main bit... | 03/20/2001 |
| 6188598 | Reducing impact of coupling noise An integrated circuit comprising a first bitline pair 310 on a first bitline level which is adjacent to a second bitline pair 320 on a second bitline level is provided. The first bitline pair comprises m twists 340, where m is a whole numberࣙ1 and the s... | 02/13/2001 |
| 6169696 | Method and apparatus for stress testing a semiconductor memory Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substant... | 01/02/2001 |
| 6157588 | Semiconductor memory device having hierarchical word line structure First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD sig... | 12/05/2000 |
| 6154395 | Semiconductor memory device having a layout pattern adjusted input terminal capacitance An object of the invention is to provide a semiconductor memory device suppressing variations in input terminal capacitances of address input terminals and control signal input terminals and enabling a high-speed access. The invention arranges a plurality... | 11/28/2000 |
| 6064588 | Embedded dram with noise-protected differential capacitor memory cells A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in ch... | 05/16/2000 |
| 6034879 | Twisted line techniques for multi-gigabit dynamic random access memories An interconnection array is provided including a plurality of line conductors having segments substantially parallel to each other in each of two or more parallel regions such that the composite length of the segments essentially matches said length of th... | 03/07/2000 |
| 5999467 | Method and apparatus for stress testing a semiconductor memory Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substant... | 12/07/1999 |
| 5986961 | Semiconductor integrated circuit of low power consumption type A semiconductor integrated circuit of a low power consumption type has modules (1) to which various supply voltages are provided. In each module (1), cells (3) are grouped into cell rows or cell columns. Only one of a wire (7) of a high supply voltage and... | 11/16/1999 |
| 5970010 | Semiconductor memory device Controlling the timing for the overdrive of the sense amplifiers in response to the wiring length between the sense amplifiers and the power supply voltage supply nodes, and designing a reduction of the power consumption by preventing excessive overdrive ... | 10/19/1999 |
| 5886919 | Multi-port semiconductor memory device with reduced coupling noise A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacen... | 03/23/1999 |
| 5883839 | Waveform stabilizing drive circuit for modularized memory A memory drive circuit includes at least one memory module constructed of a plurality of memory elements, a memory controller for driving said memory module, and a buffer, disposed between the memory module and the memory controller, for receiving a drive... | 03/16/1999 |
| 5848017 | Method and apparatus for stress testing a semiconductor memory Circuitry stress tests a Dynamic Random Access Memory (DRAM) by connecting a sense amplifier of the DRAM to at least two pairs of complementary bitlines within the same sub-array of the DRAM through two pairs of isolation transistors activated at substant... | 12/08/1998 |
| 5773892 | Multi-port semiconductor memory device with reduced coupling noise A semiconductor memory device has two complementary pairs of bit lines coupled to the same memory cells. According to a first aspect of the invention, the bit lines in one complementary pair cross over, so that each bit line in the first pair runs adjacen... | 06/30/1998 |
| 5732010 | Dynamic random access memory device with the combined open/folded bit-line pair arrangement A semiconductor memory device of the present invention comprises a plurality of word lines formed on a substrate, a plurality of bit lines perpendicular to the word lines and divided into bit-line groups in the column direction along the word line, each g... | 03/24/1998 |
| 5602772 | Dynamic semiconductor memory device A dynamic semiconductor memory device according to the present invention, comprises a plurality of first bit lines, a plurality of second bit lines which are partially laminated above the first bit lines and, together with the first bit lines, form bit-li... | 02/11/1997 |
| 5567963 | Multi-bit data storage location A multi-bit data storage location 201 is formed at the face of a layer 502 of semiconductor of a first conductivity type. Storage location 201 includes a first transistor 210 having a source/drain region 308 of a second conductivity type formed in layer 5... | 10/22/1996 |
| 5468985 | Semiconductor device There is provided a semiconductor device having a wiring configuration which can suppress an increase in the delay time of a wiring extending over the memory cell area even if the cell size is reduced. Wirings of preset wiring length are formed over a sem... | 11/21/1995 |
| 5430686 | Semiconductor memory device and operating method thereof In a DRAM, buffer circuits constituting a column address buffer are provided near address input pads receiving external address signals to be input thereto, and switch circuits arranged near the address input pads are connected between the address input p... | 07/04/1995 |
| 5420816 | Semiconductor memory apparatus with configured word lines to reduce noise According to this invention, a semiconductor apparatus includes a word line group consisting of four word lines, a bit line pair group, word line drive circuits, arrangement patterns of which are alternately inverted, for outputting boosted word line sign... | 05/30/1995 |
| 5406512 | Semiconductor memory device using compensation capacitors The semiconductor device of the present invention utilizes pairs of compensation capacitors serially connected between corresponding pairs of bit lines and interconnected to a ground line of a sense amplifier driver, so that the transistional potential ch... | 04/11/1995 |
| 5327392 | Semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise A semiconductor integrated circuit includes a circuit block whose operation is controlled by a inverted control signal whose significant potential level is set at a ground potential, and a wiring for transmitting a control signal for controlling the opera... | 07/05/1994 |
| 5319600 | Semiconductor memory device with noise immunity A semiconductor integrated circuit device chip mounts a group of voltage amplifier circuits and a group of output transistors on the surface thereof. The group of voltage amplifier circuits are arranged at an area remote from the group of output transisto... | 06/07/1994 |
| 5297094 | Integrated circuit memory device with redundant rows A dual-port memory device is provided which has a memory array divided approximately in half. The bit lines for the array are crossed over between array halves in order to minimize stray capacitance and cross-coupling capacitance for the device. Redundant... | 03/22/1994 |
| 5255231 | Architecture of realizing balance of bit line sense amplifier in DRAM cell array The present invention provides an architecture of a DRAM cell array having a plurality of bit lines and word lines. The word lines are formed by arranging metal word lines on poly-silicon word lines in parallel, and two bit lines construct a column. The m... | 10/19/1993 |
| 4870619 | Memory chip array with inverting and non-inverting address drivers A memory arrangement is comprised of a plurality of memory chips, and address and control lines connected to the chips. In order to minimize the effect of interference of signals from the address lines on the control lines, the address lines coupled to a ... | 09/26/1989 |
| 4482825 | Semiconductor device having a circuit for generating a voltage higher than a supply voltage and responsive to variations in the supply voltage In a semiconductor device having a signal line on which a voltage higher than the voltage supply is generated, a conductive layer following the potential variance of the voltage supply is positioned under an insulating film directly below the signal line ... | 11/13/1984 |
| 4339760 | Magnetic printing head having a high signal-to-noise ratio The signal-to-noise ratio as measured by the ratio of the full select magnetic field levels to the half select magnetic field levels, is improved in a coincident current magnetic printing head by providing means for producing a bias magnetic field which i... | 07/13/1982 |
| 4151608 | Circuit arrangement for suppressing magnetic induction noise due to an alternating magnetic field A third conductor is added to a pair of first and second parallel conductors transmitting signals, a part of which conductors are located in an alternating magnetic field. The three conductors are so arranged that the first and third conductors are symmet... | 04/24/1979 |
| 3942164 | Sense line coupling reduction system The inductive and capacitive coupling between adjacent sense lines in a semi-conductor memory is minimized by periodically interchanging the locations of the two sense lines assigned to each column of storage cells in a semi-conductor memory.... | 03/02/1976 |
