Bizarre Patents
A sealed crustless sandwich for providing a convenient sandwich without an outer crust which can be stored for long periods of time without a central filling from leaking outwardly.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8014219 | Semiconductor memory device A semiconductor memory device includes a memory cell having a resistance which differs based on stored data, a bit line connected to the memory cell, a first MOSFET which clamps the bit line to a read voltage when reading data, a sense amplifier which detects the st... | 09/06/2011 |
| 7936628 | Semiconductor memory and method for operating a semiconductor memory A semiconductor memory having read amplifier strips having a plurality of read amplifiers and having memory cell fields which have a plurality of memory cells connected to bit lines is disclosed. The read amplifier strips include at least two outer read amplifier st... | 05/03/2011 |
| 7929365 | Memory structure, programming method and reading method therefor, and memory control circuit thereof A memory structure that improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a refere... | 04/19/2011 |
| 7864611 | One-transistor type DRAM A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arra... | 01/04/2011 |
| 7710808 | Semiconductor memory device including a static memory cell A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the fir... | 05/04/2010 |
| 7646657 | Semiconductor memory device having replica circuit A semiconductor memory device includes a memory cell array, word line, row decoder, bit line, sense amplifier, dummy cell array, dummy bit line, sense amplifier activation circuit, and signal interconnection. The word line is connected to memory cells arrayed in the... | 01/12/2010 |
| 7630261 | Nand-structured flash memory A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end o... | 12/08/2009 |
| 7630262 | One-transistor type dram A one-transistor type DRAM includes a floating body storage element connected between a bit line and a source line and controlled by a word line. The DRAM comprises a plurality of source lines and word lines arranged in a row direction, a plurality of bit lines arra... | 12/08/2009 |
| 7593275 | Semiconductor memory device According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line ... | 09/22/2009 |
| 7499358 | Method and circuitry to generate a reference current for reading a memory cell, and device implementing same There are many inventions disclosed herein. In one aspect, the present inventions are directed to methods and circuitry to control, adjust, determine and/or modify the absolute and/or relative positioning or location (i.e., absolute or relative amount) of reference ... | 03/03/2009 |
| 7495984 | Resistive memory devices including selected reference memory cells A Resistance based Random Access Memory (ReRAM) can include a current reference circuit including at least three ReRAM reference cells coupled in parallel with one another and configured to provide a reference current to respective ReRAM sense amplifier circuits. | 02/24/2009 |
| 7471581 | Wide dynamic range and high speed voltage mode sensing for a multilevel digital non-volatile memory A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by... | 12/30/2008 |
| 7443753 | Memory structure, programming method and reading method therefor, and memory control circuit thereof The memory structure improves a sensing accuracy of memory cells by dividing the main array into a number of memory units and sensing memory cells of each memory units with an appropriate set of reference currents. Each of the memory units corresponds to a reference... | 10/28/2008 |
| 7440353 | Floating body control in SOI DRAM A system and method wherein a DRAM memory device on an integrated circuit (IC) uses a control logic device to initiate a body refresh operation for maintaining a low voltage at a floating body and discourage data loss. A plurality of DRAM cells are connected to a fi... | 10/21/2008 |
| 7433253 | Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamp... | 10/07/2008 |
| 7414908 | Magnetic memory device A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding p... | 08/19/2008 |
| 7414909 | Nonvolatile semiconductor memory There is provided a high-density mask ROM operable at a high speed. With the mask ROM, respective source lines are disposed so as to be shared by memory cells in respective columns adjacent to each other, and bit lines are disposed so as to correspond to the respect... | 08/19/2008 |
| 7411816 | Enhanced MRAM reference bit programming structure An MRAM circuit includes an MRAM array having a plurality of operational MRAM elements and a reference cell made up of one or more reference MRAM elements. A plurality of program lines within a first region are cladded with a flux-concentrating layer configured to f... | 08/12/2008 |
| 7408833 | Simulating a floating wordline condition in a memory device, and related techniques A memory device and methods to exploit extra or dummy wordlines in the memory device, wherein the extra wordlines are not part of a main memory area of the memory device but, when activated, connect their attached memory cells to the bitlines of the main memory area... | 08/05/2008 |
| 7403441 | Power management unit for a flash memory with single regulation of multiple charge pumps A power management unit for a non-volatile memory device is proposed. The power management unit includes means for providing a reference voltage, resistive means for deriving a reference current from the reference voltage, means for generating a plurality of operati... | 07/22/2008 |
| 7403433 | Self timing write architecture for semiconductor memory and method for providing the same A self timing write architecture for semiconductor memory and a method for providing the same are provided. The core region of the semiconductor memory comprises of a normal memory cell array and a dummy column. The dummy column comprises of two blocks—block A and... | 07/22/2008 |
| 7403423 | Sensing scheme for low-voltage flash memory Single-ended sensing devices for sensing a programmed state of a non-volatile memory cell are adapted for use in low-voltage memory devices. Methods of their operation include precharging an input node of a single-ended sensing device to a precharge potential while ... | 07/22/2008 |
| 7400543 | Metal programmable self-timed memories A self-timed memory array is disclosed, in which segmentability and metal-programmability are supported while minimizing layout space. Self-timing row decoder circuits are placed at the top and bottom of the array adjacent to respective I/O blocks. A self-timing sig... | 07/15/2008 |
| 7400521 | Integrated circuit, memory chip and method of evaluating a memory state of a resistive memory cell An integrated circuit comprises a resistive memory cell, at least one reference cell, a first device configured to apply a predetermined read voltage to the resistive memory cell and a second device configured to apply the predetermined read voltage to the reference... | 07/15/2008 |
| 7394698 | Method and apparatus for adjusting a read reference level under dynamic power conditions A read reference determining the logical value for results read from memory is adjusted during unstable power conditions. ... | 07/01/2008 |
| 7391661 | Column redundancy system for an integrated circuit memory A memory is organized with many memory subspaces (db) each including their own read-out circuit (SA). At least one redundant column (Blred) is provided within each subspace in order to compensate for at least one defective column of said subspace. A memory con... | 06/24/2008 |
| 7388798 | Semiconductor memory device including memory cell without capacitor A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second ... | 06/17/2008 |
| 7385866 | Load-balanced apparatus of memory A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second ... | 06/10/2008 |
| 7382644 | Two terminal memory array having reference cells A memory including reference cells is provided. The memory has address decoding circuitry and an array of memory cells that are non-volatile and re-writable. Each memory cell has a two terminal memory plug that is capable of experiencing a change in resistance. Sens... | 06/03/2008 |
| 7382668 | Full-stress testable memory device having an open bit line architecture and method of testing the same A full-stress testable memory device having an open bit line architecture and a method of testing the memory device. The memory device of the invention includes dummy bit lines, and a voltage controller connected to the dummy bit lines. The voltage controller altern... | 06/03/2008 |
| 7379365 | Method and apparatus for charging large capacitances A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer ... | 05/27/2008 |
| 7379366 | Thin film magnetic memory device capable of conducting stable data read and write operations A tunnel magnetic resistive element forming a magnetic memory cell includes a fixed magnetic layer having a fixed magnetic field of a fixed direction, a free magnetic layer magnetized by an applied magnetic field, and a tunnel barrier that is an insulator film provi... | 05/27/2008 |
| 7379328 | Semiconductor device Memory blocks having memory cells which are comprised of vertical transistors and memory elements in which the resistance value is varied depending on the temperature imposed on the upper side thereof, are laminated to realize a highly-integrated non-volatile memory... | 05/27/2008 |
| 7376033 | Semiconductor device and programming method therefor There is provided a semiconductor device including regular cells (16) disposed in a regular sector (10) and connected to a word line (14), and a plurality of reference cells (26) used in reading data from the regular cells (10), wh... | 05/20/2008 |
| 7376032 | Method and apparatus for a dummy SRAM cell A dummy SRAM cell for use in a dummy bit line circuit uses the same transistors as used in a standard SRAM cell, which includes first and second subsets of transistors configured as first and second bit line output circuits. The dummy SRAM cell includes the same fir... | 05/20/2008 |
| 7375998 | Ferroelectric random access memory circuits for guarding against operation with out-of-range voltages and methods of operating same A method of operating a ferroelectric random access memory (FRAM) can include reading a low-voltage FRAM monitoring memory array and preventing a read/write-back of an FRAM memory cell array if data read from the low-voltage FRAM monitoring memory array is corrupted... | 05/20/2008 |
| 7376031 | Semiconductor memory device and method for driving semiconductor memory device A semiconductor memory device includes a memory cell including a floating body; a word line connected to a gate of the memory cell; a data bit line connected to the memory cell and transmitting the data stored in the memory cell; a reference bit line transmitting a ... | 05/20/2008 |
| 7372731 | Flash memories with adaptive reference voltages Cells of a flash memory are read by determining respective adaptive reference voltages for the cells and comparing the cells' threshold voltages to their respective reference voltages. The adaptive reference voltages are determined either from analog measurements of... | 05/13/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7372719 | DRAM semiconductor memory device with increased reading accuracy A DRAM semiconductor memory device with increased reading accuracy and a method for increasing the reading accuracy of a DRAM memory cell are provided. First and second bit lines are connected to a sense amplifier and are connected in each case to a further memory c... | 05/13/2008 |
