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| Number | Title | Issue Date |
| 8111572 | Disturb control circuits and methods to control memory disturbs among multiple layers of memory Embodiments of the invention relate generally to data storage and computer memory, and more particularly, to systems, integrated circuits and methods for controlling memory disturbs to and among multiple layers of memory that include, for example, third dimensional ... | 02/07/2012 |
| 8059480 | Semiconductor memory device A semiconductor memory device includes a plurality of memory cells configured to correspond to each of a plurality of word lines for storing data; a plurality of reference memory cells configured to include first and second magnetic memory devices, whose lower elect... | 11/15/2011 |
| 8054706 | Sensor protection using a non-volatile memory cell A method and apparatus for protecting an electrical device using a non-volatile memory cell, such as an STRAM or RRAM memory cell. In some embodiments, a memory element is connected in parallel with a sensor element, where the memory element is configured to be repe... | 11/08/2011 |
| 7969805 | Coupling methods and architectures for information processing A structure comprising (i) a first information device, (ii) a second information device, (iii) a first coupling element and (iv) a second coupling element is provided. The first information device has at least a first lobe and a second lobe that are in electrical co... | 06/28/2011 |
| 7936627 | Magnetoresistance effect element and MRAM A magnetoresistance effect element according to the present invention comprises a magnetization free layer 1 and a magnetization fixed layer 3 connected to the magnetization free layer 1 through a nonmagnetic layer 2. The magnetization fr... | 05/03/2011 |
| 7813202 | Thin-film magnetic device with strong spin polarization perpendicular to the plane of the layers, magnetic tunnel junction and spin valve using such a device A thin-film magnetic device comprises, on a substrate, a composite assembly deposited by cathode sputtering and consists of a first layer made of a ferromagnetic material with a high rate of spin polarization, the magnetization of which is in plane in the absence of... | 10/12/2010 |
| 7596045 | Design structure for initializing reference cells of a toggle switched MRAM device A design structure embodied in a machine readable medium used in a design process includes an apparatus for initializing a reference cell in a toggle switched MRAM device, with a first sense amplifier configured for performing a first read operation of the reference... | 09/29/2009 |
| 7505347 | Method for sensing a signal in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 03/17/2009 |
| 7436723 | Method for two-cycle sensing in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 10/14/2008 |
| 7436697 | Memory cell, memory using the memory cell, memory cell manufacturing method, and memory recording/reading method A memory cell having a configuration completely different from that of a memory cell of a conventional memory and having various excellent characteristics, and also a method for manufacturing the same, are provided. A memory having various excellent characteristics ... | 10/14/2008 |
| 7436698 | MRAM arrays and methods for writing and reading magnetic memory devices A non-destructive technique and related array for writing and reading magnetic memory cells, including sampling a first signal of a selected read line corresponding to select memory cells, applying a magnetic field to the select memory cells, sampling a second signa... | 10/14/2008 |
| 7433253 | Integrated circuit, method of operating an integrated circuit, method of manufacturing an integrated circuit, memory module, stackable memory module An integrated circuit has a current sense amplifier that includes a voltage comparator having a first input, a second input and an output; a first clamping device coupled between the first input of the voltage comparator and a first input signal node, a second clamp... | 10/07/2008 |
| 7414908 | Magnetic memory device A Magnetic Random Access Memory (MRAM), in which very little current flows through MTJ elements and very little voltage is applied across them, the MRAM being provided with sense-amplifiers capable of amplifying the potential difference between their corresponding p... | 08/19/2008 |
| 7405966 | Magnetic tunneling junction antifuse device An MRAM device having a plurality of MRAM cells formed of a fixed magnetic layer, a second soft magnetic layer and a dielectric layer interposed between the fixed magnetic layer and the soft magnetic layer. The MRAM cells are all formed simultaneously and at least s... | 07/29/2008 |
| 7397694 | Magnetic memory arrays A magnetic memory array. A first bit line provides a first writing magnetic field to a magnetic memory cell. A second bit line provides a second writing magnetic field to a reference magnetic memory cell. A word line provides a third writing magnetic field to the ma... | 07/08/2008 |
| 7379364 | Sensing a signal in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 05/27/2008 |
| 7376007 | Non-volatile magnetic memory device A non-volatile magnetic memory cell having a magnetic element with multiple segments which are not co-linear. Each of the segments is magnetized with a remnant magnetic field using a single write line. The segments can be magnetized in a first direction or a second ... | 05/20/2008 |
| 7372753 | Two-cycle sensing in a two-terminal memory array having leakage current A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected tra... | 05/13/2008 |
| 7372090 | Magnetic random access memory device and method of forming the same Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a m... | 05/13/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7366030 | Simultaneous read circuit for multiple memory cells A memory device including a simultaneous read circuit design for multiple memory cells on a single interconnect using a fast fourier transform analysis circuit. The simultaneous read circuit can be used with any memory type storing information as an energy-absorbing... | 04/29/2008 |
| 7362636 | Semiconductor memory device A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair; a back bias generating circuit which generates a back bias voltage to be ... | 04/22/2008 |
| 7349243 | 3-parameter switching technique for use in MRAM memory arrays Disclosed herein are various embodiments of a 3-parameter switching technique for MRAM memory cells arranged on an MRAM array. The disclosed technique alters the relationship between the disturbance margin and write margin of MRAM arrays to reduce the overall distur... | 03/25/2008 |
| 7342840 | Single transistor sensing and double transistor sensing for flash memory A single sensing transistor is selectively diode connected to a sense line that is coupled to reference cells and data cells to store a reference current or leakage currents on the gate of the sensing transistor by opening the switch to disconnect the diode connecti... | 03/11/2008 |
| 7333379 | Balanced sense amplifier circuits with adjustable transistor body bias Structures of balanced sense amplifier circuits and methods for operating the same. The structure comprises a reading circuit, which includes a first transistor and a second transistor. The first and second transistors comprise (i) a first transistor body and a seco... | 02/19/2008 |
| 7330367 | Stacked 1T-MTJ MRAM structure This invention relates to MRAM technology and new variations on MRAM array architecture to incorporate certain advantages from both cross-point and 1T-1MTJ architectures. The fast read-time and higher signal-to-noise ratio of the 1T-1MTJ architecture and the higher ... | 02/12/2008 |
| 7330390 | Noise resistant small signal sensing circuit for a memory device Apparatus and method for data sensing circuitry that uses averaging to sense small differences in signal levels representing data states. The apparatus periodically switches the coupling of input terminals and output terminals of an integrator circuit from a first c... | 02/12/2008 |
| 7321507 | Reference cell scheme for MRAM An MRAM reference cell sub-array provides a mid-point reference current to sense amplifiers. The MRAM reference cell sub-array has MRAM cells arranged in rows and columns. Bit lines are associated with each column of the sub-array. A coupling connects the bit lines ... | 01/22/2008 |
| 7313043 | Magnetic Memory Array A magnetic memory is disclosed. In one embodiment, the magnetic memory array includes a plurality of cell columns and a pair of reference cell columns, including a first reference cell column and a second reference cell column. A comparator is provided with a first ... | 12/25/2007 |
| 7313042 | Thin film magnetic memory device having an improved read operation margin A data bus is precharged to a precharge voltage before data read operation. In the data read operation, the data bus thus precharged is electrically coupled to the same voltage as the precharge voltage through a selected memory cell. A driving transistor couples the... | 12/25/2007 |
| 7292471 | Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so ... | 11/06/2007 |
| 7288967 | Differential output driver and semiconductor device having the same An embodiment of a differential output driver includes a driver to generate an inverted output signal in response to an input signal and a first control signal, and to further generate an output signal in response to an inverted input signal and a second control sig... | 10/30/2007 |
| 7286393 | System and method for hardening MRAM bits A device is connected in parallel with an MTJ structure of an MRAM bit to shunt photocurrent away from and/or limit voltage across the MTJ structure during a dose rate event. The device may include at least one transistor and/or at least one diode. One device may be... | 10/23/2007 |
| 7286429 | High speed sensing amplifier for an MRAM cell A method and circuits are disclosed for sensing an output of a memory cell having high and low resistance states. A high reference cell is in high resistance state and a low reference cell is in low resistance state. The resistance of the high reference cell in high... | 10/23/2007 |
| 7286392 | Data retention indicator for magnetic memories The present invention provides an array (20) of magnetoresistive memory elements (10) provided with at least one data retention indicator device (50). The at least one data retention indicator device (50) comprises a first magnetic elemen... | 10/23/2007 |
| 7272034 | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each of the plurality of magnetic storage cells includes at least one magnetic element and a plurality of selection trans... | 09/18/2007 |
| 7272035 | Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells A method and system for providing a magnetic memory is described. The method and system include providing a plurality of magnetic storage cells. Each of the plurality of magnetic storage cells includes a magnetic element and a selection transistor. The magnetic elem... | 09/18/2007 |
| 7269044 | Method and apparatus for accessing a memory array A memory device including first and second memory elements is provided. The first and second memory elements each have first and second electrodes. The first electrode of the first and second memory elements is a common first electrode and is located below the secon... | 09/11/2007 |
| 7257020 | Thin film magnetic memory device having redundant configuration Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory celf columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory... | 08/14/2007 |
| 7251178 | Current sense amplifier A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage ... | 07/31/2007 |
