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| Number | Title | Issue Date |
| 8130581 | Semiconductor memory device The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connect... | 03/06/2012 |
| 8031547 | Differential sense amplifier A differential sense amplifier can perform data sensing using a very low supply voltage. ... | 10/04/2011 |
| 8023351 | Semiconductor memory device A semiconductor memory device comprises: a memory cell array including a plurality of word lines, a plurality of bit line pairs containing a first bit line and a second bit line, and a plurality of memory cells; a plurality of replica bit lines formed in the same ma... | 09/20/2011 |
| 7903490 | Semiconductor memory device The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connect... | 03/08/2011 |
| 7903489 | Semiconductor device having a sense amplifier A semiconductor device in the present invention comprises pair transistors composed of a first transistor and a second transistor. The pair transistors are arrayed in a repeating pattern in the row direction. The first transistor and the second transistor are mutual... | 03/08/2011 |
| 7852688 | Efficient sense command generation In one embodiment, a memory includes: an array of memory cells arranged according to word lines and columns, each column corresponding to bit lines; a sense amplifier adapted to couple to the bit lines to sense a binary content of selected cells from the array of me... | 12/14/2010 |
| 7843751 | Semiconductor memory device comprising sense amplifier having P-type sense amplifier and N-type sense amplifiers with different threshold voltages A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality ... | 11/30/2010 |
| 7821859 | Adaptive current sense amplifier with direct array access capability A current sense amplifier can include an active load circuit having a first load device and second load device coupled in parallel to a first power supply node. A first load device and second load device can provide an impedance that varies according to a potential ... | 10/26/2010 |
| 7813201 | Differential sense amplifier A differential sense amplifier can perform data sensing using a very low supply voltage. ... | 10/12/2010 |
| 7800970 | Sense amplifier and semiconductor memory device having the same A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential outpu... | 09/21/2010 |
| 7787321 | High performance sense amplifier and method thereof for memory system A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input termin... | 08/31/2010 |
| 7724596 | Auto-zero current sensing amplifier A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and ... | 05/25/2010 |
| 7719912 | Semiconductor memory device for sensing voltages of bit lines in high speed A semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to a different unit cell array; a bit line sense amplifying unit coupled to the first bit line pair to the fourth bit... | 05/18/2010 |
| 7719913 | Sensing circuit for PCRAM applications A sensing method for a memory cell as described herein includes selecting a memory cell. A first bias applied to the memory cell induces a first response in the memory cell. A second bias applied to the memory cell induces a second response in the memory cell, the s... | 05/18/2010 |
| 7710806 | Memory device and method for improving speed at which data is read from non-volatile memory A memory device and method for improving speed at which data is read from non-volatile memory are provided, where the memory device including the non-volatile memory precharges all word lines with a predetermined precharge voltage during standby for a read operation... | 05/04/2010 |
| 7710807 | Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. T... | 05/04/2010 |
| 7692990 | Memory cell access circuit A circuit for accessing a memory cell includes a local bitline and a local sense amplifier having a plurality of transistors. The local bitline may be connect the memory cell and the sense amplifier. A first global bitline may be connected to a first one of the plur... | 04/06/2010 |
| 7684275 | Semiconductor memory devices having memory cell arrays with shortened bitlines A semiconductor memory device includes a first memory cell array that comprises first memory cells arranged in a matrix of first rows and first columns; a second memory cell array that comprises second memory cells arranged in a matrix of second rows and second colu... | 03/23/2010 |
| 7633822 | Circuit and method for controlling sense amplifier of a semiconductor memory apparatus A sense amplifier control unit include: a control unit that detects a variation in the level of an external voltage and outputs a delay time selection signal on the basis of the result of the detection. A variable delay unit delays an active signal by a delay time c... | 12/15/2009 |
| 7573755 | Data amplifying circuit for semiconductor integrated circuit A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and a data amplifier configured to amplify an input signal one time or t... | 08/11/2009 |
| 7561484 | Reference-free sampled sensing Systems and methods for extending the usable lifetime of memory cells by utilizing reference-free sampled sensing. A stimulus component applies a plurality of different stimuli to a plurality of memory cells of a memory device. A sense component senses a characteris... | 07/14/2009 |
| 7535783 | Apparatus and method for implementing precise sensing of PCRAM devices A precision sense amplifier apparatus includes a current source configured to introduce an adjustable reference current through a reference leg; a current mirror configured to mirror the reference current to a data leg, the data leg selectively coupled to a programm... | 05/19/2009 |
| 7492655 | Memory device having high speed sense amplifier comprising pull-up circuit and pull-down circuits with drivability for each A sense amplifier is constructed to reduce the occurrence of malfunctions in a memory read operation, and thus degraded chip yield, due to increased offset of the sense amplifier with further sealing down. The sense amplifier circuit is constructed with a plurality ... | 02/17/2009 |
| 7489576 | Semiconductor storage device A semiconductor storage device has first and second cell arrays including a plurality of memory cells to store data, a sense amplifier selectively connected with either one of the first and second cell arrays, a first precharge circuit to set a pair of bit lines in ... | 02/10/2009 |
| 7477561 | Semiconductor memory device A semiconductor memory device includes a memory cell array including memory cells, word lines which select the memory cells, bit lines which transfer data of the memory cells, a sense amplifier circuit which amplifies data transferred to the bit lines, a first dummy... | 01/13/2009 |
| 7466616 | Bit line sense amplifier and method thereof A bit line sense amplifier and method thereof are provided. The example bit line sense amplifier may include a sense amplifying circuit coupled between a first bit line and a second bit line. The sense amplifying circuit may be configured to amplify a voltage differ... | 12/16/2008 |
| 7457181 | Memory device and method of operating the same A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The det... | 11/25/2008 |
| 7450455 | Semiconductor memory device and driving method thereof A semiconductor memory device prevents deterioration of refresh operation caused by sensing noise and a driving method thereof. First pull-down and second pull-down voltages which are different from each other are as a pull-down voltage of a bit line sense amplifier... | 11/11/2008 |
| 7443751 | Programmable sense amplifier multiplexer circuit with dynamic latching mode Multiplexer control logic is provided for a semiconductor memory device that combines the function of programmable disconnect-state with a dynamic or dynamic latching mode that operates during self-refresh. The programmable disconnect state disconnects the sense amp... | 10/28/2008 |
| 7443752 | Semiconductor memory device amplifying data A semiconductor memory device includes an I/O line, a first sense amplifier connected to the first I/O line to amplify a signal applied on the first I/O line in response to a first control signal, a second sense amplifier for amplifying an output signal of the first... | 10/28/2008 |
| RE40552 | Dynamic random access memory using imperfect isolating transistors Apparatus and methods for controlling the sensing of bit lines which facilitates the distribution of bit line charging current to be distributed any time, and facilitates the fast raising of the sense modes to full logic levels. An embodiment is comprised of a plura... | 10/28/2008 |
| 7440355 | Semiconductor memory device The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connect... | 10/21/2008 |
| 7430150 | Method and system for providing sensing circuitry in a multi-bank memory device A method and system for providing a multi-bank memory is described. The method and system include providing a plurality of banks. Each of the plurality of banks includes at least one array including a plurality of memory cells and analog sensing circuitry. The metho... | 09/30/2008 |
| 7426150 | Sense amplifier overdriving circuit and semiconductor device using the same A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for se... | 09/16/2008 |
| 7408813 | Block erase for volatile memory A system and method for erasing a block of data in a plurality of memory cells includes clamping one of a digit line and an I/O line in a sensing circuit of a memory device to a fixed logic level. The memory cells of the block of memory cells are selected and refres... | 08/05/2008 |
| 7405988 | Method and apparatus for systematic and random variation and mismatch compensation for multilevel flash memory operation Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing trans... | 07/29/2008 |
| 7394295 | Sense amplifier The invention relates to a sense amplifier comprising the following element: a first current mirror unit coupled to a high voltage source, outputting a first current and a second current according to a first reference current, wherein the second current is twice the... | 07/01/2008 |
| 7388787 | Reference current generator In a reference current generator, a current mirror has a referent branch with a first current flowing thereon and a mirror branch to produce a second current by mirroring the first current, a first transistor is coupled to the referent branch, a second transistor is... | 06/17/2008 |
| 7385867 | Memory device and operating method thereof A method of operating a memory device adapted for determining a program/erase state of a memory cell in the memory device. The method includes applying a drain operation voltage to a drain of the memory cell so that the memory cell generates a working voltage. The w... | 06/10/2008 |
| 7385866 | Load-balanced apparatus of memory A memory device is provided. The device comprises a sense amplifier having a cell input terminal and a reference input terminal, a first sub-array coupled to the cell input terminal through a first switch and coupled to the reference input terminal through a second ... | 06/10/2008 |