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| Number | Title | Issue Date |
| 7266030 | Method for measuring offset voltage of sense amplifier and semiconductor employing the method A semiconductor memory device precisely measures the offset voltage of a bit line sense amplifier. The semiconductor memory device of the invention includes: a bit line sense amplifier for amplifying a voltage difference between a bit line and an inversion bit line,... | 09/04/2007 |
| 7263017 | AC sensing for a resistive memory Alternating current is used to sense a logic state of a memory cell that has a resistive memory element. The memory element can be in an array and a memory device can include the array and peripheral circuitry for reading or sensing each memory cell in the array. Th... | 08/28/2007 |
| 7263016 | Method and system for pre-charging and biasing a latch-type sense amplifier A method and system for pre-charging and biasing a latch-type sense amplifier are described. According to an embodiment of the invention, the data latch portion of the latch-type sense amplifier includes two cross-coupled inverters having two output nodes, and two i... | 08/28/2007 |
| 7262641 | Current differential buffer The present technique relates to a method and apparatus for operating a differential buffer. In the differential buffer, a first stage may include a differential pair configured to receive input signals and generate output signals. The first stage may also include a... | 08/28/2007 |
| 7263002 | Nonvolatile semiconductor memory device that achieves speedup in read operation A plurality of first sub-bit lines are each connected to a common source line via a corresponding first sub-bit line reset transistor with NMOS structure, and a plurality of second sub-bit lines are each connected to the common source line via a corresponding second... | 08/28/2007 |
| 7263012 | Semiconductor storage device A semiconductor storage device includes: a plurality of memory array cells (hereinafter, referred to as cells); a circuit arranged in each of the cells for precharge of each bit line of the cells to a predetermined voltage; and a circuit for comparing, for each bit ... | 08/28/2007 |
| 7260015 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 08/21/2007 |
| 7260005 | Data bus architecture for a semiconductor memory A semiconductor memory device is provided that includes memory cells, sense amplifiers, signal lines, isolating circuits, and a precharging circuit. Each signal line is coupled to an output of at least one of the sense amplifiers and each of the isolating circuits i... | 08/21/2007 |
| 7257042 | Enhanced sensing in a hierarchical memory architecture A sense amplifier circuit for sensing a logic state of a selected memory cell in a memory circuit includes a precharge circuit and a latch circuit. The precharge circuit is adapted for connection to a pair of complementary bit lines corresponding to the selected mem... | 08/14/2007 |
| 7257015 | Semiconductor memory device having a floating storage bulk region The disclosure concerns a semiconductor memory device including a plurality of transistors. Each of the transistors has a first data state having a first threshold voltage and a second data state having a second threshold voltage. A sense amplifier is provided for a... | 08/14/2007 |
| 7257026 | Non-volatile multi-level semiconductor flash memory device and method of driving same In a nonvolatile semiconductor memory device in which a plurality of threshold values are set to store multi-level data in a memory cell, bits of multi-bit data are separately written into a memory cell according to an address signal or a control signal to effect th... | 08/14/2007 |
| 7254084 | Data processing device A delay from the release of a low power consumption mode of nonvolatile memory to the restart of read operation is reduced. Nonvolatile memory which can electrically rewrite stored information has in well regions plural nonvolatile memory cell transistors having dra... | 08/07/2007 |
| 7254077 | Circuit and method for high speed sensing A circuit and method for sensing a difference between a first signal, such as a signal from the source side of a memory cell, and a second signal, such as a signal from a reference dummy cell, includes developing first and second voltages respectively in response to... | 08/07/2007 |
| 7254076 | Semiconductor memory device for improving response margin of redundancy flag signal and redundancy driving method for the same A burst mode compatible semiconductor memory device having a redundancy memory adapted to repair a normal memory is disclosed. Response margin for a redundancy flag signal and redundancy driving method is improved by sensing generation of an internal address corresp... | 08/07/2007 |
| 7254075 | Integrated circuit memory system having dynamic memory bank count and page size A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage ce... | 08/07/2007 |
| 7254052 | Memory circuit and method for reading out a memory datum from such a memory circuit The present invention relates to a memory circuit comprising a CBRAM resistance memory cell, which is connected to a bit line and a word line and has a CBRAM resistance element, the resistance of which can be set by means of a write current, in order to store an ite... | 08/07/2007 |
| 7254072 | Semiconductor memory device having hierarchically structured data lines and precharging means A semiconductor memory device is provided comprising precharge circuits corresponding to global data line pairs, but not a precharge circuit corresponding to a local data line pair. In a command waiting state, data line selection switches are controlled to be in a c... | 08/07/2007 |
| 7254061 | Memory devices using tri-state buffers to discharge data lines, and methods of operating same A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The dat... | 08/07/2007 |
| 7251175 | Very small swing high performance asynchronous CMOS static memory (multi-port register file) with power reducing column multiplexing scheme The present invention relates to a multi-port register file memory or SRAM including a plurality of storage elements and other circuitry that operate synchronously or asynchronously, and a method of making the multi-port register file memory. The storage elements ar... | 07/31/2007 |
| 7251177 | Skewed sense AMP for variable resistance memory sensing A variable resistance memory sense amplifier has a built-in offset to assist in switching the sense amplifier when a resistive memory cell is in a low resistance state. The built-in offset can be achieved by varying size, threshold voltage, associated capacity or as... | 07/31/2007 |
| 7251176 | Semiconductor memory device A semiconductor memory device includes a memory cell array which has a plurality of memory cells, a plurality of first bit line pairs which transfer data among the memory cells, a plurality of second bit line pairs disposed corresponding to the plurality of first bi... | 07/31/2007 |
| 7251178 | Current sense amplifier A high-speed current sense amplifier has complementary reference cells and load devices that eliminate capacitive mismatch contributions. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage ... | 07/31/2007 |
| 7251174 | Semiconductor memory device for low power system A semiconductor memory device for outputting or storing a data in response to inputted address and command includes a first cell array for outputting the data to one of a bit line and a bit line bar; a first reference cell block for outputting a reference signal to ... | 07/31/2007 |
| 7248505 | Flash memory device A flash memory device includes a write driver for driving a data line according to data to be written in a flash memory cell during a program period, a sense amplifier circuit for sensing and amplifying the data stored in the flash memory cell during a program verif... | 07/24/2007 |
| 7248522 | Sense amplifier power-gating technique for integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM) A sense amplifier power-gating circuit and method is disclosed which is of particular utility with respect to DRAM devices, or those incorporating embedded DRAM, and having a power-down (or Sleep) mode of operation. In accordance with a particular technique of the p... | 07/24/2007 |
| 7248512 | Semiconductor memory device having controller with improved current consumption A semiconductor memory device wherein, in order to control the current consumed in a column address counter and latch block in a read operation, delay units disposed in the column address counter and latch block perform a shifting operation according to a signal CAS... | 07/24/2007 |
| 7245554 | Integrated semiconductor memory with clock-synchronous access control An integrated semiconductor memory device includes a first input amplifier which, compared with a second input amplifier, has a lower sensitivity with regard to level fluctuations of its respective input signal. A control circuit drives a controllable switch in such... | 07/17/2007 |
| 7245549 | Semiconductor memory device and method of controlling the semiconductor memory device A semiconductor memory device is provided that can conduct the equalizing operation of bit lines with a low current consumption while maintaining a normal accessing speed and the chip area, and a control method thereof. In a semiconductor memory device of the shared... | 07/17/2007 |
| 7245529 | Dynamically tunable resistor or capacitor using a non-volatile floating gate memory cell An integrated circuit programmable resistor or programmable capacitor has a floating gate memory cell connected either in series or in parallel to a fixed resistor or a fixed capacitor. The resistance or the capacitance of the floating gate memory cell can be change... | 07/17/2007 |
| 7245544 | Integrated semiconductor memory device including sense amplifiers An integrated semiconductor memory device includes a memory cell array with sense amplifiers that are combined in groups within the memory cell array. Each sense amplifier is associated with one data connection, the association varying on the basis of area within th... | 07/17/2007 |
| 7242615 | Non-volatile semiconductor memory device A non-volatile semiconductor memory device includes: a memory cell array with electrically rewritable and non-volatile memory cells arranged therein; a data hold circuit configured to hold read data or write data of the memory cell array; a data bit detection circui... | 07/10/2007 |
| 7242619 | Reading circuit and method for a nonvolatile memory device Described herein is a reading circuit for a nonvolatile memory device, wherein the currents flowing through an array memory cell to be read, and a reference memory cell with known contents, are converted into an array voltage and, respectively, into a reference volt... | 07/10/2007 |
| 7242628 | Semiconductor device with sense amplifier for memory cells A configuration is provided with: memory cell arrays, sense amplifiers, bit lines that connect the memory cells and sense amplifiers, and transfer gates that are inserted on the bit lines for ON/OFF control of the connections of the memory cells and the sense amplif... | 07/10/2007 |
| 7243180 | Semiconductor memory device with bus driver circuit configured to transfer an output on a common bus onto an output bus with inversion or no inversion A semiconductor memory device includes first to third data buses, and first and second connection circuits. The first connection circuit inverts and transfers a first output signal on the first data bus read out from a memory onto the second data bus in response to ... | 07/10/2007 |
| 7242629 | High speed latch circuits using gated diodes A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal... | 07/10/2007 |
| 7242627 | Semiconductor device The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sens... | 07/10/2007 |
| 7242339 | Programmable reference voltage generator A reference generator circuit has a resistor string between the potentials of the power supply voltage that is partitioned into a top string, a middle string, and a bottom string. PFET devices are used to couple the positive power supply voltage a selected node of t... | 07/10/2007 |
| 7242602 | Semiconductor memory devices having conductive line in twisted areas of twisted bit line pairs A semiconductor memory device includes spaced apart twisted bit line pairs, a respective one of which includes a spaced apart twisted area. A conductive line overlaps the respective twisted areas of the spaced apart twisted line pairs. The conductive line can extend... | 07/10/2007 |
| 7242174 | Digital sensing circuit A digital sensing circuit capable of sensing bit information stored in a bit cell of an organic memory is provided. The digital sensing circuit includes a current-to-voltage converter, a reset block circuit, and a sensing block circuit. The current-to-voltage conver... | 07/10/2007 |
| 7239537 | Method and apparatus for current sense amplifier calibration in MRAM devices A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second p... | 07/03/2007 |
