Quotables
"To place a man in a multi-stage rocket and project him into the controlling gravitational field of the moon where the passengers can make scientific observations, perhaps land alive, and then return to earth--all that constitutes a wild dream worthy of Jules Verne. I am bold enough to say that such a man-made voyage will never occur regardless of all future advances."
Lee deForest, American radio pioneer ; 1957
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| Number | Title | Issue Date |
| 7376030 | Memory sensing circuit and method for low voltage operation A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a... | 05/20/2008 |
| 7372713 | Match sensing circuit for a content addressable memory device A Content Addressable Memory (CAM) device with an improved match sensing circuit is provided. The CAM is provided with a dummy cell and a respective dummy match line, as well as a reference dummy match line. The dummy match line is designed to be evaluated after all... | 05/13/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7372715 | Architecture and method for NAND flash memory A NAND memory architecture arranges all even bitlines of a page together, and arranges all odd bitlines of a page together, so that programming operations are carried out on adjacent bitlines on the same word line to reduce floating gate coupling. Non-connected bitl... | 05/13/2008 |
| 7372725 | Integrated circuit having resistive memory A memory device including a memory cell, a first circuit, and a second circuit. The memory cell includes phase-change material. The first circuit is configured to provide pulses to the phase-change material and to program each of more than two states into the memory... | 05/13/2008 |
| 7372763 | Memory with spatially encoded data storage In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written ... | 05/13/2008 |
| 7372737 | Nonvolatile memory and method of driving the same The nonvolatile memory according to the present invention can precisely read information included in a memory transistor subject to a shift phenomenon because electrical read is performed on the memory transistor by using a reference voltage generated from a refresh... | 05/13/2008 |
| 7372762 | Semiconductor memory device The present invention is related to a semiconductor memory device improving refresh performance by reliably generating an internal voltage. The internal voltage generator for use in the semiconductor memory device includes a cell plate voltage generator, a driving v... | 05/13/2008 |
| 7369450 | Nonvolatile memory having latching sense amplifier and method of operation A memory comprises a sense amplifier for sensing a logic state of a selected bitline. The sense amplifier includes a first precharge circuit, a current-to-voltage converter, a latch circuit, and a second precharge circuit. The first precharge circuit is for precharg... | 05/06/2008 |
| 7366047 | Method and apparatus for reducing standby current in a dynamic random access memory during self refresh A dynamic random access memory including a first dynamic random access memory cell, a second dynamic random access memory cell to be refreshed, a sense amplifier, and a control circuit. The control circuit is configured to isolate the sense amplifier from at least o... | 04/29/2008 |
| 7366046 | DRAM density enhancements In one embodiment, a sense amplifier includes: a differential amplifier adapted to amplify a voltage difference between a pair of bit lines; and a self-bias generation circuit adapted to reduce an offset bias in the differential amplifier with regard to the amplific... | 04/29/2008 |
| 7366001 | Content addressable memory including main-match lines and sub-match lines The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (c... | 04/29/2008 |
| 7366002 | Method and storage device for the permanent storage of data It is proposed that bitline inversion coding data be integrally stored in the structure of a column multiplexer of a storage device. For this purpose, connections to a predefined potential are selectively provided at connection points, which are respectively assigne... | 04/29/2008 |
| 7366041 | Input buffer for low voltage operation An input buffer having differential amplifiers for receiving input signals to generate an output signal. The input buffer operates with a relatively low supply voltage and a relatively wide range of input signal levels while improving the symmetry between rising and... | 04/29/2008 |
| 7362619 | Data strobe synchronization circuit and method for double data rate, multi-bit writes A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates... | 04/22/2008 |
| 7362631 | Semiconductor memory device capable of controlling drivability of overdriver A semiconductor memory device capable of controlling a drivability of an overdriver is provided. The semiconductor memory device includes: a first power supply for supplying a normal driving voltage; a memory cell array block; a bit line sense amplifier block for se... | 04/22/2008 |
| 7362602 | Sense amplifier circuit and method A sense amplifier circuit can be coupled to a match line for receiving a match line voltage and to a low potential line for receiving a low potential voltage from a memory array. The sense amplifier circuit can include a charging circuit coupled between a power supp... | 04/22/2008 |
| 7362616 | NAND flash memory with erase verify based on shorter evaluation time A non-volatile memory device is proposed. The non-volatile memory device includes a plurality of memory cells each one having a programmable threshold voltage, and means for reading a set of selected memory cells with respect to a plurality of reference voltages, fo... | 04/22/2008 |
| 7362623 | Semiconductor memory device A semiconductor memory device includes: a memory cell array having a plurality of memory cells arranged therein; and a sense amplifier circuit configured to read data of the memory cell array, wherein a comparison operation is performed between read out data from th... | 04/22/2008 |
| 7362636 | Semiconductor memory device A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair; a back bias generating circuit which generates a back bias voltage to be ... | 04/22/2008 |
| 7362637 | Current switching sensor detector A sensor for a switching circuit detects the logical state of the switching circuit by monitoring the current flow through the switching circuit. The current flow is conditioned by one or more current limiters and a voltage regulator, coupled in series with the swit... | 04/22/2008 |
| 7362638 | Semiconductor memory device for sensing voltages of bit lines in high speed The present invention relates to a semiconductor memory device for sensing voltages of bit lines in high speed. The semiconductor memory device for sensing voltages of bit lines in high speed includes: a first bit line pair to a fourth bit line pair each coupled to ... | 04/22/2008 |
| 7359266 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 04/15/2008 |
| 7359267 | Method of transferring data A method of storing data includes transferring first data from a data line to a first sense amplifier, transferring the first data from the first sense amplifier to a first bit line, and transferring second data from the data line to a second sense amplifier. In the... | 04/15/2008 |
| 7359246 | Memory device with a ramp-like voltage biasing structure based on a current generator A memory device includes a plurality of memory cells each one for storing a value, at least one reference cell, biasing means for biasing a set of selected memory cells and the at least one reference cell with a biasing voltage having a substantially monotone time p... | 04/15/2008 |
| 7355914 | Methods and apparatuses for a sense amplifier Various apparatuses and methods in which a sense amplifier circuit couples to a current source to provide current for the sense amplifier circuit and also couples to one or more memory cells to sense a charge being stored by each memory cell. Store protection circui... | 04/08/2008 |
| 7355898 | Integrated circuit and method for reading from resistance memory cells A method and apparatus for reading from a memory arrangement, in particular, for reading from a CBRAM or another memory arrangement based on resistively switching memory cells includes charging a bit line to a voltage value, discharging the bit line by a cell resist... | 04/08/2008 |
| 7355913 | Semiconductor memory device A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing vol... | 04/08/2008 |
| 7353316 | System and method for re-routing signals between memory system components A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub c... | 04/01/2008 |
| 7352215 | High speed latch comparators In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and appli... | 04/01/2008 |
| 7352649 | High speed array pipeline architecture A memory device including a memory array having a plurality of memory cells, and a plurality of peripheral devices for reading data out of and writing data into the memory array, the peripheral devices include a first write driver connected to a first input/output l... | 04/01/2008 |
| 7352626 | Voltage regulator with less overshoot and faster settling time A voltage regulator may include an operational-amplifier section, a capacitor connected to an output of the operational-amplifier section, and a switch configured to connect the capacitor to a voltage supply. The switch is configured to charge the capacitor before a... | 04/01/2008 |
| 7352646 | Semiconductor memory device and method of arranging a decoupling capacitor thereof A semiconductor memory device with improved operational performance by reducing the level variation of first and second power voltages applied to a sense amplifier by efficiently locating a decoupling capacitor. The decoupling capacitor is arranged on an empty regio... | 04/01/2008 |
| 7349266 | Memory device with a data hold latch A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line ... | 03/25/2008 |
| 7349274 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 03/25/2008 |
| 7349283 | Integrated semiconductor memory An integrated semiconductor memory includes a test mode control circuit and at least one voltage generator for generating an operating voltage that is fed into memory banks via interconnects. Comparator circuits are arranged at locations along the respective interco... | 03/25/2008 |
| 7349264 | Alternate sensing techniques for non-volatile memories The present invention presents a scheme for sensing memory cells. Selected memory cells are discharged through their channels to ground and then have a voltage level placed on the traditional source and another voltage level placed on the control gate, and allowing ... | 03/25/2008 |
| 7349275 | Semiconductor memory A system in which an overdrive period in a DRAM may be provided without providing for accurate delay time. There are provided MOS transistor TP1, capacitor C1, MOS transistor TP2, and control circuit. MOS transistor TP1 is turned on when ... | 03/25/2008 |
| 7345910 | Semiconductor device The invention provides a semiconductor device capable of reducing wasteful power consumption. The semiconductor device of the invention does not require a refresh operation, and includes memory circuits for storing data, arranged in a matrix form, first signal lines... | 03/18/2008 |
| 7345939 | Sense amplifiers having MOS transistors therein with different threshold voltages and/or that support different threshold voltage biasing A sense amplifier includes a pair of sense bit lines and first and second MOS sense amplifiers. The first MOS sense amplifier has a first pair of MOS transistors of first conductivity type therein, which are electrically coupled across the pair of sense bit lines. T... | 03/18/2008 |
