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Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 7209393 | Semiconductor memory device and method for multiplexing write data thereof A semiconductor memory device including a write multiplexer unit that multiplexes write data transmitted to a global I/O bus disposed in front of a write driver. The semiconductor memory device further includes a memory core region including an array of memory cells... | 04/24/2007 |
| 7209405 | Memory device and method having multiple internal data buses and memory bank interleaving A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of int... | 04/24/2007 |
| 7209399 | Circuit and method of driving bitlines of integrated circuit memory using improved precharge scheme and sense-amplification scheme Provided are a bitline driving circuit of an integrated circuit memory that enhances a precharge scheme and a sense amplification scheme and a bitline driving method. In the bitline driving circuit, a new scheme of precharging the bitlines to voltages greater than o... | 04/24/2007 |
| 7205682 | Internal power supply circuit An internal power supply circuit for a semiconductor integrated circuit includes two constant voltage generators having identical circuit topologies but generating two different constant voltages from an external power supply voltage. The lower constant voltage is s... | 04/17/2007 |
| 7206240 | Fast sensing scheme for floating-gate memory cells Sensing circuits are adapted for faster sensing of a programmed state of a floating-gate memory cell. The sensing circuits include a first precharging path for applying a first precharge potential to the input node of a sensing device for precharging bit lines prior... | 04/17/2007 |
| 7206232 | Semiconductor device and source voltage control method The precharge circuit is provided for precharging, before programming the data, the voltage of the source line ARVSS commonly connected to the memory cells provided in the same sector. The voltage of the source line ARVSS of the memory cell MC is precharged before p... | 04/17/2007 |
| 7206234 | Input buffer for low voltage operation Some embodiments of the invention include an input buffer having multiple differential amplifiers for receiving input signals to generate an output signal. The input buffer operates in a relatively low supply voltage and a relatively wide range of signal levels of t... | 04/17/2007 |
| 7203123 | Integrated DRAM memory device An integrated memory device including a number of memory blocks including memory cells wherein the memory cells are arranged in a matrix of wordlines and bitlines, wherein the number of memory blocks including a first set of memory blocks the memory cells thereof ha... | 04/10/2007 |
| 7203102 | Semiconductor memory having tri-state driver device A semiconductor memory having at least one memory cell adapted to store a data value, and adapted to be connected to a data line through a switch device controlled by a control signal. The invention also relates to a tri-state driver device for driving the control s... | 04/10/2007 |
| 7203127 | Apparatus and method for dynamically controlling data transfer in memory device Methods and apparatus for operating a secondary sense amplifier according to different timings. Embodiments of the invention generally provide a secondary sense amplifier configured to dynamically adjust its timing according to a need for data in an output buffer. I... | 04/10/2007 |
| 7200029 | Ferroelectric storage device A ferroelectric storage device includes a ferroelectric capacitor C1, a bit line BL, a first switching element 103 selectively connecting the ferroelectric capacitor C1 and the bit line BL, a first transistor 203 connected to the bit line... | 04/03/2007 |
| 7200064 | Apparatus and method for providing a reprogrammable electrically programmable fuse An apparatus and method for providing a reprogrammable electrically programmable fuse (eFuse) are provided. With the apparatus and method, a pair of eFuses are provided coupled to programming current sources and sensing current sources. When the pair of eFuses is to... | 04/03/2007 |
| 7200061 | Sense amplifier for semiconductor memory device A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line d... | 04/03/2007 |
| 7196945 | Semiconductor memory A semiconductor memory has a plurality of memory cells having a single-ended digit structure. When reading data from a selected memory cell, a digit voltage outputted from the selected memory cell is compared with a reference voltage. If the digit voltage is higher,... | 03/27/2007 |
| 7196953 | Semiconductor device using high-speed sense amplifier Disclosed is a sense amplifier arrangement that achieves high-speed access and shorter cycle time when array voltage is lowered in a DRAM. In a TG clocking sense system to separate data lines between the array side and the sense amplifier side in an early stage of a... | 03/27/2007 |
| 7196954 | Sensing current recycling method during self-refresh A bit line sensing scheme is provided for a semiconductor memory device that significantly reduces current drain during a self-refresh mode. After bit line sensing of a selected wordline and deactivation of the selected wordline, a capacitor is connected to a source... | 03/27/2007 |
| 7193925 | Low power semiconductor memory device A low power semiconductor memory device can reduce power consumption of the whole chip by activating a bit line sense amplifier and a sub word line driver for driving a selected memory cell array block. The low power semiconductor memory device comprises a plurality... | 03/20/2007 |
| 7193913 | Sense amplifier circuit and read/write method for semiconductor memory device A sense amplifier circuit comprising a local I/O line pair, a global I/O line pair, a write amplification unit for amplifying and transferring data output from the global I/O line pair to the local I/O line pair in response to a first control signal, and a read ampl... | 03/20/2007 |
| 7193912 | Semiconductor integrated circuit device A DRAM whose operation is sped up and power consumption is reduced is provided. A pair of precharge MOSFETs for supplying a precharge voltage to a pair of input/output nodes of a CMOS sense amplifier is provided; the pair of input/output nodes are connected to a com... | 03/20/2007 |
| 7187601 | Active termination circuit and method for controlling the impedance of external integrated circuit terminals An active termination circuit is used to set the input impedance of a plurality of input terminals. Each of the input terminals is coupled to a supply voltage through at least one PMOS transistor and to ground through at least one NMOS transistor. The impedances of ... | 03/06/2007 |
| 7184296 | Memory device A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to th... | 02/27/2007 |
| 7184304 | Nonvolatile semiconductor memory device and method for fabricating the same A semiconductor memory device includes: first and second bit cells for storing complementary data; a scan circuit for outputting a selected data signal; a bit-cell selector receiving the output of the scan circuit and selecting one of the bit cells; and a data write... | 02/27/2007 |
| 7184290 | Logic process DRAM A dynamic random access memory (DRAM) unit includes pluralities of bit line pairs and word lines. Each bit line pair includes first and second bit lines aligned with each other in an end-to-end arrangement. The first bit lines are arranged substantially parallel and... | 02/27/2007 |
| 7184344 | Semiconductor device comprising a differential sense amplifier, a write column selection switch and a read column selection switch A semiconductor device includes a differential sense amplifier connected to a bit line, and a data transfer circuit including a column selection switch for turning ON/OFF the connection between a data line and the bit line. The semiconductor device incorporates one ... | 02/27/2007 |
| 7184348 | Sensing circuit for a semiconductor memory A sensing circuit is provided for sensing semiconductor memory cells. The sensing circuit includes at least one first circuit branch, a feedback-controlled circuit element in the first circuit branch, a current-to-voltage conversion circuit in the first branch, and ... | 02/27/2007 |
| 7183795 | Majority voter apparatus, systems, and methods Apparatus and systems, as well as methods and articles, may operate to provide a majority voter indication using a sense amplifier coupled to a first plurality of bit inputs and to a second plurality of bit inputs. ... | 02/27/2007 |
| 7184347 | Semiconductor memory devices having separate read and write global data lines Semiconductor memory devices include a memory cell array region having a plurality of memory cells, a local data I/O line pair that is electrically connected to the plurality of memory cells, a local sense amplifier that is electrically connected to the local data I... | 02/27/2007 |
| 7184343 | Nonvolatile semiconductor memory device providing stable data reading A nonvolatile semiconductor memory device includes a first memory cell having a conductive/nonconductive state thereof substantially controlled in response to data stored therein and providing passage of a first current amount in the conductive state, a first bit li... | 02/27/2007 |
| 7184345 | High speed and high precision sensing for digital multilevel non-volatile memory system A digital multilevel non-volatile memory includes a massive sensing system that includes a plurality of sense amplifiers disposed adjacent subarrays of memory cells. The sense amplifier includes a high speed load, a wide output range intermediate stage and a low imp... | 02/27/2007 |
| 7183811 | Comparing circuit, comparator, level determining circuit and threshold voltage setting method In a comparing circuit, an input signal switching circuit has a first input terminal, a second input terminal, a first output terminal and a second output terminal. The input signal switching circuit is configured to receive a first input signal inputted to the firs... | 02/27/2007 |
| 7184323 | 4N pre-fetch memory data transfer system A semiconductor storage device has a data transfer circuit capable of reducing the latency, including a control circuit for frequency-dividing external clock signal to generate readout clocks, first to fourth amplifier circuits for amplifying read data corresponding... | 02/27/2007 |
| 7180765 | Ferroelectric memory A ferroelectric memory including a ferroelectric capacitor to store data; a bit line inputting and outputting data with respect to the ferroelectric capacitor; a control circuit having a first field effect transistor to be connected to the bit line and a reference p... | 02/20/2007 |
| 7180793 | Semiconductor non-volatile storage device A semiconductor non-volatile storage device of the present invention which lets a memory cell directly drive up to a local bit line, wherein the output of the local bit line is received by a gate electrode of a separately-provided signal amplifying transistor, and t... | 02/20/2007 |
| 7180814 | Low power circuits with small voltage swing transmission, voltage regeneration and wide bandwidth architecture An integrated circuit, such as a memory macro, includes multiple power rails supporting first and second voltage differentials, with the second voltage differential being smaller than the first voltage differential. Signal lines in the integrated circuit are driven ... | 02/20/2007 |
| 7180804 | High performance sense amplifier and method thereof for memory system A system and method for sensing a current. The system includes an operational amplifier including a first input terminal, a second input terminal, and a first output terminal. The first input terminal is biased to a predetermined voltage, and the second input termin... | 02/20/2007 |
| 7177201 | Negative bias temperature instability (NBTI) preconditioning of matched devices An accumulated data-dependent post-manufacture shift in a characteristic of one or more of a pair of matched devices within an integrated circuit may cause a mismatch in the characteristic between the pair of matched devices. This mismatch may be reduced by precondi... | 02/13/2007 |
| 7176087 | Methods of forming electrical connections In one aspect, the invention provides a method of forming an electrical connection in an integrated circuitry device. According to one preferred implementation, a diffusion region is formed in semiconductive material. A conductive line is formed which is laterally s... | 02/13/2007 |
| 7176728 | High voltage low power driver A power driver circuit is provided including a low voltage source, a high voltage source, at least one input signal line, an output node, and circuitry adapted to connect the output node to the low voltage source when the input signal line is in a first state and to... | 02/13/2007 |
| 7177217 | Method and circuit for verifying and eventually substituting defective reference cells of a memory A circuit verifies and substitutes a defective reference cell of a memory device that includes at least one reference current path including the reference cell and a decoding transistor connected in series. The circuit includes at least one redundant reference curre... | 02/13/2007 |
| 7173457 | Silicon-on-insulator sense amplifier for memory cell A silicon-on-insulator (SOI) sense amplifier for sensing bit values stored in a memory cell, includes first and second input field effect transistors (FETs), connected to first and second cross-coupled CMOS inverter FET pairs. The input FETs are implemented as float... | 02/06/2007 |
