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| Number | Title | Issue Date |
| 8189415 | Sensing amplifier applied to at least a memory cell, memory device, and enhancement method for boosting the sensing amplifier thereof A sensing amplifier consists of a sensing circuit, a boosting circuit, at least one bit-line isolating circuit, and at least a P-sensing enhancement circuit. The sensing circuit is disposed between a sensing line and a complementary sensing line. The boosting circui... | 05/29/2012 |
| 8189416 | Semiconductor memory device The semiconductor memory device includes a first memory cell connected between a first word line and a bit line. The semiconductor memory device may also include a second memory cell connected between a second word line and an inverted bit line. Additionally, the me... | 05/29/2012 |
| 8174920 | Semiconductor memory device and driving method of the same A memory includes a first and a second bit lines (BL); a first and a second sense nodes (SN); a first transfer gate between the 1st-BL and the 1st-SN; a second transfer gate (TG) between the 2nd-BL and the 2nd-SN; a latch ... | 05/08/2012 |
| 8169845 | Apparatus and methods for sense amplifiers Some embodiments include apparatus and methods having a sense amplifier unit, a supply node to receive a supply voltage, and a line coupled to a memory cell of a device. The sense amplifier unit includes a circuit path coupled between the supply node and the line to... | 05/01/2012 |
| 8149640 | Differential sense amplifier The differential sense amplifier according to one aspect of the present invention includes a first differential amplification unit that detects a difference between the pair of complementary signals inputted from a first bit line and a second bit line, a second diff... | 04/03/2012 |
| 8130580 | Low power sense amplifier for reading memory A low power sense amplifier is configured to sense the state of a memory cell (e.g., non-volatile memory cell) without the use of a reference current or direct current. ... | 03/06/2012 |
| 8120980 | Semiconductor memory device in which a method of controlling a BIT line sense amplifier is improved A semiconductor memory device includes a sense amplifier, a sense amplifier driving signal driver, and a controller. The sense amplifier is configured to sense and amplify a signal of a bit line and a signal of a complementary bit line in response to a sense amplifi... | 02/21/2012 |
| 8116158 | Semiconductor device guaranteeing stable operation A semiconductor device includes a data line pair formed of a data line and a complementary data line; a first sensing amplification unit including a first sensing amplifier and a second sensing amplifier that are cross-coupled with the data line and the complementar... | 02/14/2012 |
| 8111571 | Semiconductor memory device A semiconductor memory device comprises a plurality of word lines, a plurality of bit lines intersecting the word lines, a memory cell array having a plurality of memory cell each provided at an intersection of the word line and the bit line, a plurality of sense am... | 02/07/2012 |
| 8107308 | Semiconductor memory device A semiconductor memory device is provided. A memory cell array has a plurality of memory cells connected between a plurality of word lines and a plurality of bit-line pairs. A sense amplifier unit has a plurality of sense amplifiers connected with the bit-line pairs... | 01/31/2012 |
| 8102726 | Semiconductor device A semiconductor device includes a plurality of memory cells and a sense amplifier circuit which further includes a plurality of elements such as MOS transistor formed in a well, wherein sensitive element, which are sensitive to dispersion of an impurity density in t... | 01/24/2012 |
| 8085611 | Twisted data lines to avoid over-erase cell result coupling to normal cell result Over-erasure induced noise on a data line in a nonvolatile memory that couples into an adjacent data line is mitigated by using twisted data lines and differential sensing amplifiers. Noise coupled into data lines is compensated by similar noise coupled into referen... | 12/27/2011 |
| 8081530 | Semiconductor memory device and associated local sense amplifier A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to... | 12/20/2011 |
| 8072828 | Sense amplifier circuit and semiconductor memory device A single-ended sense amplifier circuit comprises first and second MOS transistors and first and second voltage setting circuits. The first MOS transistor supplies a predetermined voltage to the bit line and switches connection between the bit line and a sense node i... | 12/06/2011 |
| 8050126 | Non-volatile memory with improved sensing by reducing source line current One or more sense amplifiers for sensing the conduction current of non-volatile memory is controlled by signals that are timed by a reference sense amplifier having similar characteristics and operating conditions. In one aspect, a sensing period is determined by wh... | 11/01/2011 |
| 8036058 | Symmetrically operating single-ended input buffer devices and methods Embodiments are described including those pertaining to an input buffer having first and second complementary input terminals. One such input buffer has a symmetrical response to a single input signal applied to the first input terminal by mimicking the transition o... | 10/11/2011 |
| 8027214 | Asymmetric sense amplifier Sensing circuits for determining the state of memory cells include a sense amplifier. The sense amplifier includes an imbalanced cross-coupled latch (ICL), a first gate field effect transistor (FET) between a bit line (BL) and a first output node, and a second gate ... | 09/27/2011 |
| 8014221 | Memory devices including floating body transistor capacitorless memory cells and related methods A semiconductor memory device includes a memory cell array which includes a plurality of unit memory cells, where each of the unit memory cells comprises complementary first and second floating body transistor capacitor-less memory cells. A logic value written into ... | 09/06/2011 |
| 8009496 | Semiconductor device including asymmetric sense amplifier A semiconductor device includes an alternating arrangement of memory cell blocks and sense amplifier blocks, such that the sense amplifier blocks include an interior sense amplifier block and a periphery amplifier block. The peripheral amplifier block includes a fir... | 08/30/2011 |
| 7995411 | Sensing and latching circuit for memory arrays According to one exemplary embodiment, a memory sensing and latching circuit includes a sensing circuit for evaluating bit lines in a memory array and providing a sensed output. The memory sensing and latching circuit further includes a latching circuit including a ... | 08/09/2011 |
| 7990791 | Semiconductor memory device A memory includes a cell array; bit lines; word lines; sense amplifiers; first determination transistors receiving information data and making a connection between a first voltage source and a first determination node be in a conductive or a non-conductive state bas... | 08/02/2011 |
| 7990792 | Hybrid sense amplifier and method, and memory device using same Sense circuits, devices and methods are disclosed, including a sense amplifier circuit that has first and second complementary data lines and a sensing circuit. One of the data lines can be coupled to a memory cell for data sensing and the other data line can be use... | 08/02/2011 |
| 7978552 | Semiconductor memory device A memory includes memory cells, wherein during a first write operation in which first logical data is written in all memory cells connected to a first word line, a source line driver and a word line driver, the source line driver shifts a voltage of a selected sourc... | 07/12/2011 |
| 7961538 | Methods for determining resistance of phase change memory elements Methods for measuring the resistance of multiple memory elements are disclosed. The memory elements may be multi-bit memory and through precise measurement of resistance of the multi-bit memory elements, determination of how many and which memory elements fall into ... | 06/14/2011 |
| 7948811 | Memory with shared read/write circuit A memory includes memory cells arranged as a matrix of rows and columns between word lines and bit lines, and a set of differential read/write amplifiers for reading and writing of the memory cells and for communicating with local bit lines common to at least some o... | 05/24/2011 |
| 7944766 | Sense amplifier and semiconductor memory device having sense amplifier A sense amplifier comprises: a differential amplifier circuit configured to generate an amplified signal depending on a difference in voltage between bit lines; an output circuit receiving the amplified signal; and a load. The differential amplifier circuit comprise... | 05/17/2011 |
| 7936626 | Sense amplifier with a compensating circuit A sense amplifier for a memory includes a transistor, an operational amplifier, and a compensating circuit. The negative input end of the operational amplifier is coupled to the compensating circuit. The positive input end of the operational amplifier is coupled to ... | 05/03/2011 |
| 7933160 | High speed carbon nanotube memory In order to realize high speed carbon nanotube memory, bit line is multi-divided into short lines for reducing parasitic capacitance. For reading, a small local sense amp is composed of a local pre amplifier and a local main amplifier with high gain, and a simple gl... | 04/26/2011 |
| 7924643 | Sense amplifier and driving method thereof, and semiconductor memory device having the sense amplifier The semiconductor memory device includes a bank having a cell array and a sense amplifier. A back bias voltage generating unit supplies a back bias voltage to the cell array of the bank. A negative drive voltage generating unit generates negative driving voltages in... | 04/12/2011 |
| 7911863 | Semiconductor device and DRAM controller According to a semiconductor device of the present invention, a differential potential between a sense amplification level and a precharge level of a sense amplifier is set to a power supply potential (VCC-GND) so as to improve resistance against degradation of hold... | 03/22/2011 |
| 7898887 | Sense amplifier with redundancy A sense amplifier includes a first sensing element and a second sensing element redundant to the first sensing element. The sense amplifier further comprises a switch circuit configured to switch between the first and second sensing elements when an offset of the se... | 03/01/2011 |
| 7898885 | Analog sensing of memory cells in a solid state memory device A memory device that includes a sample and hold circuit coupled to a bit line. The sample and hold circuit stores a target threshold voltage for a selected memory cell. The memory cell is programmed and then verified with a ramped read voltage. The read voltage that... | 03/01/2011 |
| 7898886 | Sense amplifiers and semiconductor devices including the same A sense amplifier includes a first transistor having a gate electrode electrically connected to a bit line and a first electrode electrically connected to a complementary bit line. A second transistor has a gate electrode electrically connected to the complementary ... | 03/01/2011 |
| 7894286 | Array sense amplifiers, memory devices and systems including same, and methods of operation A sense amplifier having an amplifier stage with decreased gain is described. The sense amplifier includes a first input/output (“I/O”) node and a second complementary I/O node. The sense amplifier includes two amplifier stages, each for amplifying a signal on o... | 02/22/2011 |
| 7889585 | Balancing a signal margin of a resistance based memory circuit A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel... | 02/15/2011 |
| 7881138 | Memory circuit with sense amplifier A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal ... | 02/01/2011 |
| 7869294 | Semiconductor device having single-ended sensing amplifier A single-ended sense amplifier in a semiconductor storage device having a hierarchical bit line structure includes a first MOS transistor for amplifying a signal outputted from a memory cell to a bit line, a second MOS transistor for feeding the output of the first ... | 01/11/2011 |
| 7869295 | Semiconductor memory apparatus A semiconductor memory apparatus includes a sense amplifier that receives a driving voltage through a sense amplifier power supply input terminal and detects and amplifies a difference between signals that are supplied to two input lines, a sense amplifier voltage s... | 01/11/2011 |
| 7864610 | Sense amplifier controlling circuit and controlling method A sense amplifier controlling circuit for controlling a sense amplifier in a semiconductor memory, which amplifies differential electric potential of a pair of bit lines to which memory cells are connected by sequentially operating a CMOS flip-flop and a preamplifie... | 01/04/2011 |
| 7864608 | Semiconductor device A semiconductor device includes a DRAM cell configured to store a data; and a sense amplifier activated in response to supply of power supply voltages and configured to sense the data stored in the DRAM cell. A power supply circuit supplies the power supply voltages... | 01/04/2011 |
