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| Number | Title | Issue Date |
| 8154938 | Memory array power domain partitioning An integrated circuit containing a nonvolatile memory circuit which contains memory segments and sense amplifier banks individually powered by a power decoder circuit. A method of accessing a portion of a powered-down memory. ... | 04/10/2012 |
| 8094510 | Memory array incorporating noise detection line A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 01/10/2012 |
| 8077534 | Adaptive noise suppression using a noise look-up table A proactive noise suppression system and method for a power supply network of an integrated circuit. The system and method include receiving an IC event sequence to a memory element, correlating the IC event sequence to a storage location in a second memory element,... | 12/13/2011 |
| 8045410 | Memory cell array A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, th... | 10/25/2011 |
| 7969804 | Memory architecture having a reference current generator that provides two reference currents A memory architecture is provided with an array of non-volatile memory cells arranged in rows and columns, and a sense amplifier coupled to at least one column within the array for sensing a data bit stored within one of the non-volatile memory cells. In order to pr... | 06/28/2011 |
| 7952948 | Semiconductor memory apparatus A semiconductor memory apparatus includes non-inversion repeaters that non-invert data and output the inverted data; and inversion repeaters that invert data and output the inverted data. The non-inversion repeaters or the inversion repeaters are arranged on a first... | 05/31/2011 |
| 7952949 | Electronic circuit that comprises a memory matrix and method of reading for bitline noise compensation Data is read from a memory matrix (10) with a plurality of bit lines (12). A differential sense amplifier (14) receives a signal derived from a first one of the bit lines (12) on a first input. The differential sense amplifier (14)... | 05/31/2011 |
| 7936630 | Method and apparatus for calibrating a read/write channel in a memory arrangement Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing dat... | 05/03/2011 |
| 7907461 | Structures and methods of preventing an unintentional state change in a data storage node of a latch A method of preventing an unintentional state change in a data storage node of a latch is disclosed. The method comprises receiving a reference input signal; generating a delayed input signal based upon the reference clock signal; maintaining a state of a first data... | 03/15/2011 |
| 7894285 | Circuits, systems, and methods for reducing simultaneous switching output noise, power noise, or combinations thereof Memory devices and methods are provided for reducing simultaneous switching output noise and power supply noise during burst data write and refresh operations. An embodiment of a memory device according to the present invention includes a first power domain coupled ... | 02/22/2011 |
| 7889584 | Semiconductor memory device having input first-stage circuit A semiconductor memory device of the present invention determines a logic level of a signal based on a predetermined reference voltage. And the memory device has an input terminal to which a reference signal having the reference voltage is input, a low-pass filter c... | 02/15/2011 |
| 7800967 | Semiconductor memory device and driving method thereof This disclosure concerns a memory including: word lines extending to a first direction; bit lines extending to a second direction crossing the first direction; a memory cell array including cell blocks each including memory cells respectively provided corresponding ... | 09/21/2010 |
| 7773442 | Memory cell array latchup prevention A complementary field-effect (CMOS) circuit is provided which includes a current-limiting device arranged along a power-supply bus or a ground bus of the circuit. The current-limiting device is configured to prevent latch up of the CMOS circuit. More specifically, t... | 08/10/2010 |
| 7773443 | Current sensing method and apparatus for a memory array A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 08/10/2010 |
| 7768844 | Nonvolatile semiconductor memory device and method of driving the same This disclosure concerns a memory including memory cell arrays including word lines extending in a first direction, bit lines extending in a second direction crossing the first direction, and memory cells provided to respectively correspond to cross-points in form o... | 08/03/2010 |
| 7764556 | Semiconductor storage device including counter noise generator and method of controlling the same A semiconductor storage device according to one aspect of the present invention includes a reference voltage source connected to a capacitor of a cell included in a memory, a buffer circuit holding data to be written in the cell, and a counter noise generator output... | 07/27/2010 |
| 7719911 | Semiconductor storage device A semiconductor storage device is provided which enables use of an overdrive method at low voltage and for a small device area. The semiconductor device includes: memory cells; sense amplifiers, each having P-channel and N-channel MOS transistors and amplifying a si... | 05/18/2010 |
| 7649793 | Channel estimation for multi-level memories using pilot signals Embodiments of the present invention provide channel estimation for multi-level memories using pilot signals. A memory apparatus includes a memory block comprising a plurality of memory cells and adapted to operate with at least two levels of signals for writing dat... | 01/19/2010 |
| 7636268 | Integrated circuit with improved static noise margin A static random access memory (“SRAM”) has a plurality of SRAM cells connected to a word line. A static noise margin (“SNM”) detector controls a pull-down transistor that selectively couples the word line to a ground path. The SNM detector is configured to p... | 12/22/2009 |
| 7613058 | Radiation hardening, detection and protection design methods and circuit examples thereof Radiation hardening, detection and protection design methods are disclosed. An example write drive circuit is disclosed having radiation hardened analog circuitry. A passive transistor is provided to generate a radiation photo-current to offset any net radiation pho... | 11/03/2009 |
| 7577045 | Semiconductor memory device A semiconductor memory device includes transistors that supply a higher write potential and a lower write potential to a sense amplifier, respectively, an overdrive transistor that supplies an overdrive potential to the sense amplifier, and a control circuit that ch... | 08/18/2009 |
| 7570530 | Nonvolatile memory device using variable resistive element Disclosed is a nonvolatile memory device using a variable resistive element, and a data read circuit for use in variable resistive memory devices. More specifically, embodiments of the invention provide a data read circuit with one or more decoupling units to remove... | 08/04/2009 |
| 7548475 | Apparatus of processing a signal in a memory device and a circuit of removing noise in the same A circuit for removing noise from an input signal includes a falling edge signal delaying circuit configured to output a first delay output signal generated by delaying a falling edge of a first output signal for a preset time; a falling edge sensing circuit configu... | 06/16/2009 |
| 7505344 | Current sensing method and apparatus particularly useful for a memory array of cells having diode-like characteristics A memory array includes a sensing circuit for sensing bit line current while keeping the voltage of the selected bit line substantially unchanged. The word lines and bit lines are biased so that essentially no bias voltage is impressed across half-selected memory ce... | 03/17/2009 |
| 7426150 | Sense amplifier overdriving circuit and semiconductor device using the same A sense amplifier overdriving circuit includes a first voltage driver which supplies an internal voltage from an internal voltage terminal to a sense amplifier in response to a first enabling signal, a logic unit which logically operates a block select signal for se... | 09/16/2008 |
| 7426148 | Method and apparatus for identifying short circuits in an integrated circuit device The disclosed embodiments relate to a method and apparatus for identifying short circuits in an integrated circuit device. The method may comprise the acts of programming a first memory cell associated with a first digit line to a first data value, programming a sec... | 09/16/2008 |
| 7400541 | Circuits and methods for data bus inversion in a semiconductor memory A data bus inversion (DBI) circuit includes at least one DBI block configured to invert an input data signal based on the logic state of input data bits. The DBI block includes a comparison deciding unit configured to generate, in a first mode, a comparison signal b... | 07/15/2008 |
| 7400544 | Actively driven Vfor input buffer noise immunity A memory device including a circuit for actively driving a reference voltage in a memory device is disclosed. A circuit integrated in a memory device and coupled to an external voltage source substantially eliminates fluctuations in the reference voltage of the memo... | 07/15/2008 |
| 7391666 | DRAM power bus control A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power ... | 06/24/2008 |
| 7385864 | SRAM static noise margin test structure suitable for on chip parametric measurements A set of memory cell test structures and a method for assessing of the static noise margin (SNM) of a memory cell or cells, using discrete point measurement structures provided either on-chip or within the scribe lines. A set of memory structures may comprise first ... | 06/10/2008 |
| 7372717 | Methods for resistive memory element sensing using averaging A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage su... | 05/13/2008 |
| 7366006 | SRAM with read assist A Static Random Access Memory (SRAM) matrix with a read assist is described. The read assist reduces the probability associated with an SRAM matrix becoming upset by a radiation event. Each SRAM cell within the SRAM matrix includes an active delay for increasing Sin... | 04/29/2008 |
| 7362636 | Semiconductor memory device A semiconductor memory device comprising: a sense amplifier which includes a pair of first NMOS transistors and a pair of PMOS transistors connected to a bit line pair as a complementary pair; a back bias generating circuit which generates a back bias voltage to be ... | 04/22/2008 |
| 7359273 | Semiconductor memory device having layout for minimizing area of sense amplifier region and word line driver region A semiconductor memory device has a layout that minimizes the area required for sense amplifier and word line driver regions. In the semiconductor memory device of the present invention, decoding drivers are arranged in sense amplifier regions. Further, the wiring f... | 04/15/2008 |
| 7359268 | Semiconductor memory device for low voltage A semiconductor memory device includes a read amplifying unit for transferring a data from a local data line pair to a global data line as a read data; a write driver for transferring a write data from the global data line to the local data line pair; and an input/o... | 04/15/2008 |
| 7355904 | Method and apparatus for drain pump operation A method and apparatus are provided for improved noise reduction from switching on and off drain pumps (202) in a high voltage generator. The drain pumps (202) are divided into groups (204) and activation of the groups (204) of drain pump... | 04/08/2008 |
| 7349266 | Memory device with a data hold latch A memory device includes a plurality of pairs of complimentary bit lines and a plurality of latch circuits. Each pair of the plurality of pairs of complimentary bit lines is coupled to a column of memory cells. Each latch circuit has an input coupled to a data line ... | 03/25/2008 |
| 7349270 | Semiconductor memory with wordline timing A semiconductor memory with wordline timing, which links activating a wordline to an isolation signal. The isolation signal is applied to a memory section adjacent the memory section containing the wordline to be activated. Upon such an isolation signal shifting low... | 03/25/2008 |
| 7349274 | Precharge circuit and method employing inactive weak precharging and equalizing scheme and memory device including the same Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit l... | 03/25/2008 |
| 7350018 | Method and system for using dynamic random access memory as cache memory A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the ... | 03/25/2008 |
