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| Number | Title | Issue Date |
| 7940590 | Electronic device comprising non volatile memory cells and corresponding programming method A device with non volatile memory cells, with optimized programming, of the type comprising a sector of matrix memory cells organized in rows and columns, with the columns organized in a plurality of global bit-lines associated with at least one plurality of local b... | 05/10/2011 |
| 7940581 | Method for low power sensing in a multi-port SRAM using pre-discharged bit lines A method for sensing the contents of a memory cell within a static random access memory (SRAM) includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being accessed; energizing the bit line to a first volt... | 05/10/2011 |
| 7936619 | Nonvolatile memory, memory system, and method of driving Provided are a nonvolatile memory and related method of programming same. The nonvolatile memory includes a memory cell array with a plurality of nonvolatile memory cells and a write circuit. The write circuit is configured to write first logic state data to a first... | 05/03/2011 |
| 7903488 | Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device Voltage coupling/decoupling devices are provided within DRAM devices for improving the bias sensing of sense amplifiers and thus the refresh performance. The voltage coupling/decoupling devices couple or decouple bias voltage from corresponding digit lines coupled t... | 03/08/2011 |
| 7864607 | Negative voltage discharge scheme to improve snapback in a non-volatile memory Charge pump and discharge circuitry for a non-volatile memory device that splits up the discharge operation into two discharge periods. In a first discharge period, the voltage being discharged (e.g., erase voltage) is discharged through a pair of discharge transist... | 01/04/2011 |
| 7830727 | Apparatus and method for low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines An apparatus and method for low power, single-ended sensing in a multi-port static random access memory (SRAM) using pre-discharged bit lines includes holding a bit line associated with the memory cell at a zero voltage potential when the memory cell is not being ac... | 11/09/2010 |
| 7453750 | Flash memory device with word line discharge unit and data read method thereof Exemplary embodiments of the present invention provide a flash memory device which includes a memory cell array. A decoder circuit is connected to the memory cell array via a plurality of select lines and a plurality of word lines. The detector circuit supplies volt... | 11/18/2008 |
| 7443706 | High-performance memory and related method In memory array of a memory circuit, a discharging module and an auxiliary module are disposed on each column line. While accessing an objective memory unit on a column line of the memory, the memory unit discharges the corresponding row line of the objective memory... | 10/28/2008 |
| 7443749 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 10/28/2008 |
| 7443750 | Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets A switched capacitor sense amplifier includes capacitively coupled input, feedback, and reset paths to provide immunity to the mismatches in transistor characteristics and offsets. The sense amplifier includes a cross-coupled pair of inverters with capacitors absorb... | 10/28/2008 |
| 7443712 | Memory erase management system A memory erase management system is provided, including providing a resistive change memory cell, coupling a first line to the resistive change memory cell, coupling a line buffer to the first line, providing a charge storage device coupled to the line buffer, and p... | 10/28/2008 |
| 7436721 | Supplying voltage to a bit line of a memory device A method supplies voltage to a bit line of a memory device. The method includes precharging, with a precharging device, the bit line to an output potential, deactivating the precharging device during a read action related to the bit line, reading, during the read ac... | 10/14/2008 |
| 7428169 | Nonvolatile semiconductor memory device and voltage generating circuit for the same A nonvolatile semiconductor memory device includes a memory cell array of a plurality of memory cells; and a voltage generating circuit for generating a programming voltage to be applied to the memory cells. The voltage generating circuit includes a first voltage ge... | 09/23/2008 |
| 7426131 | Programmable memory device circuit Circuits for writing, reading, and erasing a programmable metallization cell are disclosed. The programming circuits compensate for parasitic capacitance and/or parasitic resistance. The parasitic resistance and/or capacitance is compensated for using a feedback loo... | 09/16/2008 |
| 7411849 | Apparatus and method for transferring an analog signal between isolated systems An apparatus and method for transferring a signal from a first bus circuit to a second bus circuit. The apparatus and method includes a first constant current circuit connected to the first bus circuit, a first capacitor connected between the first bus circuit and t... | 08/12/2008 |
| 7408811 | NAND-type flash memory on an SOI substrate with a carrier discharging operation A semiconductor memory device includes: a semiconductor layer provided on an insulating substrate or an insulating layer; active areas each defined in the semiconductor layer with a device insulating film buried therein; and NAND cell units formed on the active area... | 08/05/2008 |
| 7382657 | Semiconductor memory device having bit line precharge circuit controlled by address decoded signals A semiconductor memory device includes a memory cell array, a charge circuit which compensates for OFF leakage current developed at selected bit lines, a reset circuit having a ground potential corresponding to a potential at non-selected bit lines, a read circuit c... | 06/03/2008 |
| 7379340 | Sense amplifier circuit in non-volatile semiconductor memory comprising a boosting capacitor for boosting the potential at sense node A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from ... | 05/27/2008 |
| 7379333 | Page-buffer and non-volatile semiconductor memory including page buffer In one aspect, a non-volatile memory device is provided which is operable in a programming mode and a read mode. The memory device includes a memory cell array which includes a plurality of non-volatile memory cells, a plurality of word lines, and a plurality of bit... | 05/27/2008 |
| 7379354 | Methods and apparatus to provide voltage control for SRAM write assist circuits Methods and apparatus to control voltage output of a write assist circuit are disclosed. An example method includes regulating pull down voltage from a write assist circuit having a write assist capacitor coupled to a discharge node coupled to a bit line. The write ... | 05/27/2008 |
| 7376030 | Memory sensing circuit and method for low voltage operation A sensing module operates with a sense amplifier sensing a conduction current of a memory cell via a coupled bit line under constant voltage condition in order to minimize bit-line to bit-line coupling. The rate of discharge of a dedicated capacitor as measured by a... | 05/20/2008 |
| 7372739 | High voltage generation and regulation circuit in a memory device An auxiliary voltage generation circuit is part of a high voltage generation and regulation circuit. The auxiliary voltage generation circuit generates an auxiliary intermediate voltage that is coupled to a negative level shifting circuit to reduce the drain-source ... | 05/13/2008 |
| 7355876 | Memory array circuit with two-bit memory cells A high-speed nonvolatile memory array has two-bit memory cells, each connected to a mutually adjacent pair of sub-bit lines. The sub-bit lines are connected to a common power supply line through switching elements controlled in a cyclic sequence by 2m signal lines, ... | 04/08/2008 |
| 7352645 | Memory device A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated w... | 04/01/2008 |
| 7339839 | Triggering of IO equilibrating ending signal with firing of column access signal A method and apparatus for improving time between row address latching and column address latching (tRCD) by allowing the pull-up of the IO lines during a READ burst to end upon the firing of a column access signal rather than waiting for the next clock signal of th... | 03/04/2008 |
| 7336552 | Sense amplifier connecting/disconnecting circuit arrangement and method for operating such a circuit arrangement An apparatus and method for operating a sense amplifier connecting/disconnecting circuit arrangement, in particular for a semiconductor memory device, including a switching device for connecting/disconnecting a sense amplifier to/from a bit line of a first cell fiel... | 02/26/2008 |
| 7333370 | Method to prevent bit line capacitive coupling Structures, systems and methods for memory cells utilizing trench bit lines formed within a buried layer are provided. A memory cell is formed in a triple well structure that includes a substrate, the buried layer, and an epitaxial layer. The substrate, buried layer... | 02/19/2008 |
| 7324394 | Single data line sensing scheme for TCCT-based memory cells A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge ... | 01/29/2008 |
| 7310257 | Local digit line architecture and method for memory devices having multi-bit or low capacitance memory cells A DRAM array includes for each column a pair of complimentary digit lines that are coupled to a sense amplifier. Each of the global digit lines is selectively coupled to a plurality of local digit lines by respective coupling circuits. The length of the local digit ... | 12/18/2007 |
| 7301826 | Memory, processing system and methods for use therewith A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column ena... | 11/27/2007 |
| 7292483 | Back-bias voltage generator for decreasing a current consumption of a self-refresh operation An internal voltage generator for generating a back bias voltage includes a back bias voltage pumping block for comparing a reference voltage with a feedback back bias voltage to generate a back bias enable signal and the back bias voltage in response to an activate... | 11/06/2007 |
| 7289371 | Semiconductor memory device and electronic equipment A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a wri... | 10/30/2007 |
| 7289376 | Method for eliminating crosstalk in a metal programmable read only memory The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, ... | 10/30/2007 |
| 7280407 | Semiconductor memory device including floating gates and control gates, control method for the same, and memory card including the same A semiconductor memory device includes memory cells, a memory cell array, word lines, a first charge pump circuit, and a discharge circuit. The memory cell has a first MOS transistor with a stacked gate including a floating gate and a control gate. The memory cell a... | 10/09/2007 |
| 7280401 | High speed data access memory arrays Techniques for reading data from memory cells in memory arrays are provided. Local read bit lines are coupled to logic gates such as NAND gates. The input terminals of each logic gate are coupled to receive signals from two of the local read bit lines. The output of... | 10/09/2007 |
| 7277327 | Methods for erasing flash memory Methods for erasing flash memory using a decrease in magnitude of a source voltage of a first polarity to increase the magnitude of a control gate voltage of a second polarity during an erase period. ... | 10/02/2007 |
| 7272060 | Method, system, and circuit for performing a memory related operation A method, system, and circuit for performing a memory related operation are disclosed. An operating voltage is applied to a bitline and a neighboring bitline is precharged. The precharge voltage has a magnitude less than the operating voltage. Both voltages ramp up ... | 09/18/2007 |
| 7263014 | Semiconductor memory device having N-bit prefetch type and method of transferring data thereof A semiconductor memory device in which only global I/O buses, which receive one or more data groups that must be output first among a N number of data groups that are prefetched in a N-bit prefetch type, from an array of memory cells are precharged with a ½ power s... | 08/28/2007 |
| 7257040 | Fast pre-charge circuit and method of providing same for memory devices A fast pre-charge circuit and method of providing a fast pre-charge for an integrated circuit memory device is disclosed. The fast pre-charge circuit comprises an address calculating unit and a multi-power driver. The address calculating unit detects the sector dist... | 08/14/2007 |
| 7254061 | Memory devices using tri-state buffers to discharge data lines, and methods of operating same A memory device includes a sense amplifier circuit, a tri-state buffer, a data latch circuit and a data line. The sense amplifier circuit senses and amplifies a current of a memory cell. The tri-state buffer receives an output of the sense amplifier circuit. The dat... | 08/07/2007 |
