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| Number | Title | Issue Date |
| 7304895 | Bitline variable methods and circuits for evaluating static memory cell dynamic stability Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM... | 12/04/2007 |
| 7301850 | Content addressable memory (CAM) devices having bidirectional interface circuits therein that support passing word line and match signals on global word lines Content addressable memory devices include a bidirectional interface circuit configured to receive word line signals from a plurality of global word lines and pass match information from a selected one of a plurality of CAM arrays to the plurality of global word lin... | 11/27/2007 |
| 7301838 | Sense amplifier circuitry and architecture to write data into and/or read from memory cells A technique of, and circuitry for sampling, sensing, reading and/or determining the data state of a memory cell of a memory cell array (for example, a memory cell array having a plurality of memory cells which consist of an electrically floating body transistor). In... | 11/27/2007 |
| 7301826 | Memory, processing system and methods for use therewith A memory includes a selected bitline coupled to the array of memory cells. A column voltage booster produces a boosted column enable signal. A column multiplexer passes a signal on the selected bitline as a sense amplifier input in response to the boosted column ena... | 11/27/2007 |
| 7301842 | Synchronous pseudo static random access memory A latency control circuit for use in a semiconductor memory device includes a precharge unit for outputting a precharge reset signal based on a refresh signal and a normal active signal, wherein the precharge reset signal is used for extending a latency during a bur... | 11/27/2007 |
| 7301819 | ROM with a partitioned source line architecture A partitioned source line architecture for reducing leakage and power in a ROM. In one embodiment, a ROM is comprised of a plurality of storage cells organized as an array having M rows and N columns. Each column is associated with a precharged source line that is p... | 11/27/2007 |
| 7298655 | Isolation control circuit and method for a memory device A semiconductor memory includes a memory cell array, a sense amplifier, an isolation device interposed between the sense amplifier and a bit line of the memory cell array, and circuitry for transferring a charge contained in a memory cell of memory cell array to the... | 11/20/2007 |
| 7295481 | Power saving by disabling cyclic bitline precharge A method and system of accessing memory cells within a dynamic hardware memory block operated with a bitline precharge circuit, in which differential read/write access operations are performed by activating complementary bitlines. A reduction in power dissipation is... | 11/13/2007 |
| 7295463 | Phase-changeable memory device and method of manufacturing the same A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage... | 11/13/2007 |
| 7295469 | Nonvolatile semiconductor memory device with a ROM block settable in a write/erase inhibit mode A memory cell array has a first and a second storage area. The first storage area has a memory elements selected by an address signal. The second storage area has a memory elements selected by a control signal. A control circuit has a fuse element. When the fuse ele... | 11/13/2007 |
| 7295482 | Semiconductor memory device for a low voltage operation A semiconductor memory includes first and second cell arrays for applying a data signal onto pairs of first bit lines and second bit lines, respectively, first and second reference cell blocks each of which applies a reference signal onto a corresponding bit line ba... | 11/13/2007 |
| 7292471 | Semiconductor memory device having a voltage-controlled-oscillator-based readout circuit By first readout, the current input from a selected cell is converted by a preamplifier and a VCO into pulses of a frequency inversely proportionate to the current value, and the number of the pulses within a preset time interval is counted by a counter 5 so ... | 11/06/2007 |
| 7292481 | Semiconductor storage device There is provided a semiconductor storage device capable of executing a high-speed read operation without increasing a chip area thereof. The semiconductor storage device includes per-bit sensing circuits 103 each connected to a pair of bit lines (BLT, BLN) a... | 11/06/2007 |
| 7292495 | Integrated circuit having a memory with low voltage read/write operation An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line ... | 11/06/2007 |
| 7289376 | Method for eliminating crosstalk in a metal programmable read only memory The present invention provides a method for eliminating crosstalk (coupling noise) in a metal programmable read only memory. The metal programmable read only memory comprises a plurality of bit lines, a plurality of word lines, a plurality of precharge transistors, ... | 10/30/2007 |
| 7289355 | Pre-written volatile memory cell A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 o... | 10/30/2007 |
| 7289378 | Reconstruction of signal timing in integrated circuits Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows ... | 10/30/2007 |
| 7289351 | Method of programming a resistive memory device In an embodiment of a method of programming a resistive memory device, an electrical potential is applied to the gate of a transistor operatively associated with the resistive memory device, and successive, increasing electrical potentials are applied across the res... | 10/30/2007 |
| 7289382 | Rewritable fuse memory An apparatus includes a first fuse, a second fuse and a circuit. The circuit uses the first fuse to indicate a stored value for a fuse memory location, and in response to the fuse memory location being rewritten, the circuit uses the second fuse to indicate the stor... | 10/30/2007 |
| 7289370 | Methods and apparatus for accessing memory In a first aspect, a first method is provided for accessing memory. The first method includes the steps of (1) storing a bit in a cell included in a memory having a plurality of cells arranged into rows and columns, wherein each cell includes a group of transistors ... | 10/30/2007 |
| 7289373 | High performance memory device A memory device is provided comprising a memory array consisting of a plurality of memory cells. These memory cells are accessed via a plurality of word lines and a plurality of bit lines. Multiplexer logic is provided which has the plurality of bit lines connected ... | 10/30/2007 |
| 7286425 | System and method for capacitive mis-match bit-line sensing Dynamic random access memory (DRAM) sensing is accomplished by using capacitive mismatch between a bit line without a cell and a corresponding bit line with a cell to determine if a selected capacitor holds a one or a zero. Isolators on the bit lines are used to cre... | 10/23/2007 |
| 7286430 | Semiconductor device A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first ... | 10/23/2007 |
| 7286427 | Integrated semiconductor memory device with test circuit for sense amplifier An integrated semiconductor memory device includes sense amplifiers that are connected to in each case one bit line pair via controllable voltage generators. In a test mode state, precharging voltages can be fed to at least one of the bit lines of each one of the bi... | 10/23/2007 |
| 7286428 | Offset compensated sensing for magnetic random access memory An offset compensated memory element voltage supply including a differential amplifier with a compensation circuit, and a transistor with a gate connected to the output of the differential amplifier. The compensation circuit of the differential amplifier includes a ... | 10/23/2007 |
| 7286423 | Bit line precharge in embedded memory An integrated circuit device includes a first latch having a first input to receive a first predecode value, a second input to receive a first clock signal, and an output to provide a latched first predecode value responsive to an edge event of the first clock signa... | 10/23/2007 |
| 7286383 | Bit line sharing and word line load reduction for low AC power SRAM architecture In a SRAM structure, space and power saving is achieved by providing row and column select lines to select a specific bit cell, and reducing the number of bit lines in the structure used for writing to and reading from the bit cells. The number of bit lines is reduc... | 10/23/2007 |
| 7285986 | High speed, low power CMOS logic gate A logic gate with a differential evaluation stage, precharge circuitry for precharging outputs of the gate, latch circuitry for latching the outputs and an inverter. The gate uses high speed, low threshold voltage devices in the evaluation stage, yet uses higher thr... | 10/23/2007 |
| 7286424 | Semiconductor integrated circuit device A semiconductor device includes signal lines over which signals are transferred, and a drive circuit driving the signal lines in operating modes. The operating modes include a dynamic operation mode in which the signal lines are precharged, and a static operation mo... | 10/23/2007 |
| 7286382 | Segmented dataline scheme in a memory with enhanced full fault coverage memory cell testability A memory includes a plurality of row segments, with each row segment having a number of memory cells coupled to a corresponding dataline segment pair. Dataline driver circuits are provided between row segments to buffer signals on adjacent dataline segments. A contr... | 10/23/2007 |
| 7283411 | Flood mode implementation for continuous bitline local evaluation circuit A method, an apparatus, and a computer program product are provided for flood mode implementation of SRAM cells that employ a continuous bitline local evaluation circuit. Flood mode testing is used to weed out marginal SRAM cells by stressing the SRAM cells. Flood m... | 10/16/2007 |
| 7283412 | Bit line sense amplifier and semiconductor memory device having the same There is provided a semiconductor memory device that can calculate an offset voltage of a bit line sense amplifier. The semiconductor memory device includes a cell array, an edge bit line sense amplifier for amplifying data of an edge cell array, and a power supply ... | 10/16/2007 |
| 7283418 | Memory device and method having multiple address, data and command buses A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by ... | 10/16/2007 |
| 7280422 | BLEQ driving circuit in semiconductor memory device A bit line equalization signal (BLEQ) driving circuit for generating an equalization signal used to perform a precharge operation in a semiconductor memory device includes a second boosted voltage generator for producing a second boosted voltage by pumping a supply ... | 10/09/2007 |
| 7280401 | High speed data access memory arrays Techniques for reading data from memory cells in memory arrays are provided. Local read bit lines are coupled to logic gates such as NAND gates. The input terminals of each logic gate are coupled to receive signals from two of the local read bit lines. The output of... | 10/09/2007 |
| 7280391 | Phase change memory device for use in a burst read operation and a data reading method thereof A phase change memory device for use in a burst read operation and a data reading method are provided. The memory device includes a plurality of bit lines and a plurality of word lines. A memory cell array block has a plurality of phase change memory cells that are ... | 10/09/2007 |
| 7277011 | Removable memory media with integral indicator light A flash memory module includes an integral indicator light. The module alternatively includes a plurality electrical contacts which electrically interface to a host digital device. The module includes a plurality of flash memory cells. The cells are controlled by an... | 10/02/2007 |
| 7277322 | Semiconductor memory device having ECC circuit A semiconductor device includes a memory cell array and first and second replica bit lines. A plurality of memory cells are arranged in an array form on the memory cell array. The first replica bit line is configured by wirings having the same wiring width and wirin... | 10/02/2007 |
| 7276888 | Precharge circuit for DC/DC boost converter startup An integrated circuit including a precharge circuit for a DC/DC boost converter which includes a reference current circuit with a MOSFET transistor (MP4) that has a gate connected with the gate of the DC/DC boost converter's power MOSFET transistor (MP5 | 10/02/2007 |
| 7277356 | Methods of controlling memory modules that support selective mode register set commands A memory module may include a plurality of memory devices coupled to a memory controller over a same command/address bus. Methods of controlling such a memory module may include providing a mode register set command from the memory controller to each of the integrat... | 10/02/2007 |
