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| Number | Title | Issue Date |
| 4144590 | Intermediate output buffer circuit for semiconductor memory device A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with sense amplifier circuits at the center of each column and an intermediate output buffer having inputs connected to b... | 03/13/1979 |
| 4144589 | Precharged data line driver For use in a microprocessor on a single semiconductor chip, circuitry responsive to a timing signal and a data signal for discharging a precharged data line to correspond to the data to be transmitted on the data line. First and second enhancement-type fi... | 03/13/1979 |
| 4141081 | MNOS BORAM sense amplifier/latch A sense amplifier/latch circuit for a Metal Nitride Oxide (MNOS) Block Orgaized Random Access Memory (BORAM) with analog memory retention interrogation capabilities. The sense amplifier/latch circuit includes the associative memory transistors as an integ... | 02/20/1979 |
| 4138740 | Memory system A plurality of memory cells are connected to first and second data lines, and a circuit for applying a precharge voltage and a dummy cell are connected to each of first and second input lines which are connected to input terminal of a differential amplifi... | 02/06/1979 |
| 4133611 | Two-page interweaved random access memory configuration A random access memory (RAM) containing 256 memory cells organized as two pages, each page containing 16 8-bit wide working registers. RAM row address circuitry as well as read-write and page-select circuitry are provided. A fixed transistor static RAM ce... | 01/09/1979 |
| 4133051 | Information refreshing system in a semiconductor memory A semiconductor memory is provided with means for refreshing the memory. Interrupt requests generated by the memory initiate refreshing cycles which are uniformly distributed during periods of normal operation of the memory, each cycle for a row of the me... | 01/02/1979 |
| 4131951 | High speed complementary MOS memory A complementary MOS memory with improved access time is provided with a speed-up signal level changing circuit having two bus lines in which the signal level of the bus line on which a signal level is changing is detected dependent on the signal level dif... | 12/26/1978 |
| 4130896 | Peripheral circuit in a memory system A peripheral circuit in a memory system comprising an address buffer circuit, a driver circuit and a control circuit includes two precharge signal generating circuits, one for supplying a precharge signal to the address buffer circuit and the other for su... | 12/19/1978 |
| 4122548 | Memory storage array with restore circuit A memory storage system which utilizes semiconductor storage cells comprised of cross-coupled bipolar transistors arranged in a memory system array with an error reference circuit and a standby reference circuit that is controlled by a clock signal. The s... | 10/24/1978 |
| 4119871 | Function generator for the production of a voltage across a node to which are connected flip-flops which are arranged in bit lines of a MOS memory and consists of MOS transistors A function generator is connected to a node formed by the source electrodes of the switching transistors of flip-flops in which the flip-flops are each composed of two circuit arms. Each of the circuit arms has a load transistor and a switching transistor... | 10/10/1978 |
| 4112508 | Semiconductor memory A semiconductor memory comprises means for forcing the potential on one data line to which no writing means is connected to be set to a certain level after data have been read from a memory cell, and means for setting the level of the one data line cooper... | 09/05/1978 |
| 4112512 | Semiconductor memory read/write access circuit and method A high performance semiconductor memory read/write data access circuit including a sense amplifier directly coupled to a pair of bit lines is provided with a pair of bit switching devices to enable data communication external to the memory. Control potent... | 09/05/1978 |
| 4110840 | Sense line charging system for random access memory A random access memory includes a column of static MOS storage cells. Two sense-write conductors are coupled to each cell in the column. Each sense-write conductor is also coupled, respectively, to a termination MOSFET. The first sense-write conductor of ... | 08/29/1978 |
| 4087044 | Circuit arrangement for monitoring the function of a dynamic decoder circuit A circuit arrangement for monitoring the function of a dynamic decoder circuit which comprises at least parallel-connected decoder transistors, a pre-charging transistor, and an end stage which samples the output signal of the decoder transistors, is disc... | 05/02/1978 |
| 4085458 | Random access memory In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of m... | 04/18/1978 |
| 4082966 | MOS detector or sensing circuit A detector circuit for MOS/LSI integrated circuit devices comprises a series transistor which has a sense clock applied to its gate and a gated capacitor connected between the gate and a sense node. The sense node and an input node may be precharged to a ... | 04/04/1978 |
| 4081701 | High speed sense amplifier for MOS random access memory A random access memory device of the MOS integrated circuit type employs an array of rows and columns of one-transistor storage cells with bistable sense amplifier circuits at the center of each column. The load transistors in each bistable circuit have c... | 03/28/1978 |
| 4077031 | High speed address buffer for semiconductor memory Disclosed is an address buffer circuit for use in semiconductor memories. The buffer includes a pair of cross-coupled transistors having set and reset nodes that are precharged to a predetermined level prior to sensing the input address signals. The set a... | 02/28/1978 |
| 4070590 | Sensing circuit for memory cells A weak signal detecting circuit in which a sensing circuit formed with a flip-flop circuit, and bit lines each having connected thereto a plurality of 1-transistor type memory cells, are interconnected by separation transistors for separating them from ea... | 01/24/1978 |
| 4070656 | Read/write speed up circuit for integrated data memories An improved method of operating a monolithic memory together with novel and efficient circuitry for practicing said improved method is disclosed. In a bipolar transistor store, or monolithic memory, in accordance with the invention, a very low current (fi... | 01/24/1978 |
| 4069427 | MIS logic circuit of ratioless type An MIS logic circuit of a ratioless type comprising at least one logic section including one or more MIS FETs and provided with first and second electric energy suppressors which otherwise is fed back from output to input of the logic block through the ga... | 01/17/1978 |
| 4069474 | MOS Dynamic random access memory having an improved sensing circuit In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto are provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifi... | 01/17/1978 |
| 4069475 | MOS Dynamic random access memory having an improved sense and restore circuit In a memory circuit, first and second bit line portions, each having a plurality of memory cells coupled thereto as provided for reading and writing electrical potentials into and out of the coupled memory cells. A bistable flip-flop type sensing amplifie... | 01/17/1978 |
| 4063118 | MIS decoder providing non-floating outputs with short access time In a multiplicity of NAND decoders, each comprises a dynamic ratioless circuit including a capacitor to be charged in response to a precharge pulse, an MOS logic circuit for discharging the capacitor by an address pulse in the non-selection mode, and firs... | 12/13/1977 |
| 4061954 | Dynamic random access memory system An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a co... | 12/06/1977 |
| 4061999 | Dynamic random access memory system An integrated circuit MOSFET dynamic random access memory is disclosed which utilizes a plurality of memory cells arrayed in rows and columns. One-half of the cells in each column are connected to a true digit line and the other half are connected to a co... | 12/06/1977 |
| 4062000 | Current sense amp for static memory cell A MOSFET random access memory having a highly sensitive sense amplifier is disclosed. The sense amplifier utilizes a field effect transistor connected in the common gate mode so as to produce a large output swing on a reltively low capacitance output node... | 12/06/1977 |
| 4060740 | Sensing amplifier for capacitive MISFET memory In a sensing amplifier for a capacitive MISFET memory, the level of an output signal from the memory is shifted by a signal level shifting circuit and the level-shifted signal is applied to an input of the sensing amplifier to thereby provide a high speed... | 11/29/1977 |
| 4051388 | Flip-flop accompanied by two current switches, one having a smaller current sink capability than the other A first current switching circuit is connected to a first node of a flip-flop circuit and has an input terminal. A second current switching circuit is connected to a second node of the flip-flop and has a control terminal connected to the first node and a... | 09/27/1977 |
| 4048629 | Low power MOS RAM address decode circuit An MOS random access memory chip utilizes a column decode circuit scheme in which a signal derived from a chip select input of the random access memory chip is coupled to the gate of a switching device of dynamic IGFET NOR gates utilized to accomplish the... | 09/13/1977 |
| 4044341 | Memory array A memory array includes row conductors which have to be charged to a first level prior to each read-out cycle. During a read-out cycle the row conductors may or may not be discharged to a second level depending on whether a "1" or a "0" is stored at selec... | 08/23/1977 |
| 4042915 | MOS dynamic random access memory having an improved address decoder circuit In an MOS dynamic random access memory, address input signals are received by individual comparator buffers which generate corresponding individual pairs of complementary address signals in response to respective ones of the input address signals. The pai... | 08/16/1977 |
| 4041330 | Selectable eight or twelve digit integrated circuit calculator and conditional gate output signal modification circuit therefor An integrated circuit calculator which can operate in either a twelve digit or an eight digit mode is provided. A conditional modification circuit modifies some of the memory addresses employed in the twelve digit calculator to provide the eight digit cal... | 08/09/1977 |
| 4040015 | Complementary MOS logic circuit A dynamic complementary metal -oxide-semiconductor circuit (CMOS) includes a pair of gate stages connected in cascade. The first gate stage includes a first logic block which effects a prescribed logical function, the logic block being connected between a... | 08/02/1977 |
| 4038646 | Dynamic MOS RAM An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher ... | 07/26/1977 |
| 4031522 | Ultra high sensitivity sense amplifier for memories employing single transistor cells This disclosure relates to a high impedance regenerative differential sense amplifier for use with an integrated circuit memory array of single transistor cells. Each of the sense amplifiers is formed of a cross coupled latch connected to the respective c... | 06/21/1977 |
| 4021781 | Virtual ground read-only-memory for electronic calculator or digital processor A read-only-memory for use in an electronic calculator or the like, implemented in a large-scale-integrated MOS semiconductor chip. The ROM is designed to save space on the chip by employing a virtual ground feature and to operate fast due to a precharge ... | 05/03/1977 |
| 4016550 | Charge transfer readout of charge injection device arrays The combination of an X-Y addressed array of charge injection devides (CIDs) and a charge transfer output register system. The array is read out a row at a time by first restoring charge to the columns of the array, then removing the excess charge from th... | 04/05/1977 |
| 3993917 | Parameter independent FET sense amplifier A high speed ratioless FET sense amplifier for sensing stored information in a semiconductor memory system. The amplifier is capable of sensing very small voltage signals provided by charges stored in a plurality of single FET/capacitor memory cells. The ... | 11/23/1976 |
| 3978459 | High density MOS memory array A high density MOS integrated circuit memory array utilizing single device dynamic cells and a uniquely controlled sense amplifier. The loads of the sense amplifier are also used to precharge bit lines thereby reducing the number of devices used in prior ... | 08/31/1976 |
